New Publications are available for Analogue circuits
http://dl-live.theiet.org
New Publications are available now online for this publication.
Please follow the links to view the publication.Comparison of Euclidean distance based neural networks for analog integrated circuits fault recognition- LVQS &SOM
http://dl-live.theiet.org/content/conferences/10.1049/ic_20070676
The advent of integrated circuits (ICs) and hence the subsequent miniaturization of electronic circuitry has brought out considerable difficulties encountered during identification of faults in integrated circuits during the testing phase of manufacturing and subsequent mass production. Artificial neural network (ANN) augurs well in handling such complex tasks in such systems as it generalizes well without the need to explicitly define the relationship between variables. There has been resurgence in interest among researchers in utilizing ANN for recognizing faults in analog circuits. This work aims at analyzing the role played by the various training parts of both the Euclidean distance based ANNs namely, the self organizing feature maps(SOM) and various versions of learning vector quantization neural network (LVQNN)i.e., LVQ1, LVQ 2, LVQ 2.1 and LVQ. Extensive studies have been conducted to ascertain the role played by learning rate and other unique parameters such as the role played by normalization as a part of preprocessing technique and the number of iterations for convergence. Moreover the results have been compared with the generalized multilayer feedforward network with back propagation algorithm. The best combination of network parameters was also determined. For this purpose an analog filter circuit with 1 fault free and 10 single hard faults was simulated using SPICE simulation software. Experimental results demonstrate the high classification accuracy and the adaptability of both the Euclidean classifiers and its suitability for fault recognition in analog circuits.The design of a 4.5 GHz CMOS tuned oscillator for clock and data recovery applications
http://dl-live.theiet.org/content/conferences/10.1049/ic_20000484
Describes the design of a 4.5-GHz CMOS tuned oscillator for clock and data recovery applications which has been implemented in a 0.18μm copper CMOS ASIC process. A basic comparison has also been made between harmonic and ring oscillator circuits and the potential advantages of the harmonic oscillator for use within high frequency PLL applications has also been covered. Improvements have also been suggested in both the design and simulation of these circuits to improve the performance of future designs. (12 pages)Evolvable hardware systems using programmable analogue devices
http://dl-live.theiet.org/content/conferences/10.1049/ic_19980209
One way of exploring the use of evolution for design of analogue systems is to use an evolutionary algorithm to suggest circuits and a software simulator to test these candidates; this is usually called `extrinsic' evolution. In our work we are looking at evolution as a method for obtaining the set of instructions to apply to programmable analogue devices. These are devices which have been designed to process analogue signals, but the nature of the analogue operations that are performed on the signals are specified by the contents of digital registers on the device. Hence candidate circuits can be implemented immediately and tested on real signals, providing what is called `intrinsic' evolution. Using evolutionary methods to programme these new analogue devices has the advantage not only of providing a method of automating the design process but also allows candidate designs to be drawn from a wider repertoire of combinations than would be practical for a human designer. This may allow a given performance to be obtained from a system in a more efficient way than would otherwise have been discovered. (6 pages)Motorola field programmable analogue arrays, present hardware and future trends
http://dl-live.theiet.org/content/conferences/10.1049/ic_19980205
The Motorola MPAA020 Field Programmable Analogue Array (FPAA) is an integrated array of undedicated programmable analogue cells, based upon switched capacitor technology. Programming data is held in SRAM in each cell, and it is possible to configure and re-configure the implemented circuit without limit. The chip is capable of supporting a diverse range of analogue signal processing functions, such as data conversion, linear signal processing, filtering and non-linear functions. The MPAA020 chip is mounted within a development board which provides support functions such as clock generation, voltage regulation and I/O pins. This board connects to the serial port of a PC to provide easy download of configurations from the design support software, Easy Analog<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">TM</sup>. This software fully abstracts the design process away from component level to system level. At system level, design entry is performed by inter-connection of user-parameterised macro-cells and then downloaded directly to the device. Very rapid prototyping of switched capacitor circuits is possible with the MPAA020 array, reducing time to market by months when compared with a full custom ASIC implementation. A full configuration of the chip may be accomplished in 5 μS and a partial update of the function may be done in 200 nS per 8 bit data word. (5 pages)Circuit multi-fault diagnosis and prediction error estimation using a committee of Bayesian neural networks
http://dl-live.theiet.org/content/conferences/10.1049/ic_19971198
There is currently interest in developing the computerised diagnosis of analogue circuits. The presence of both soft faults and feedback effects make the diagnosis difficult. One approach is to measure the response of the faulty circuit to a test input signal. Faults in the circuit may cause the response to be modified. It may then be possible to diagnose the faults by digitally processing their associated responses. One technique for diagnosing the faults is to use the pattern recognition and nonlinear regression properties of multilayer perceptron (MLP) artificial neural networks. While the MLP approach yields the values of the faulty components, both accuracy of prediction and some estimation of the confidence in the predictions are needed. More accurate predictions are obtainable by training the MLPs using Bayesian methods than by using the conventional back-propagation algorithm. Confidence estimates in the predictions may be formed by computing the error bars associated with each prediction, based upon a theory of errors applicable to MLPs derived from Bayesian statistical theory. In practical terms the prediction errors may then be calculated by using a number of committees of MLPs, where each committee contains several MLPs. This technique is illustrated for the case of diagnosing multi-faults in an integrated differential amplifier. (7 pages)Analogue circuit synthesis from performance specifications
http://dl-live.theiet.org/content/conferences/10.1049/ic_19971119
Global optimisation techniques such as simulated annealing have been successfully applied to the digital synthesis problem. In this paper we describe how this technique has been applied to the synthesis of analogue circuits. To date, simulated annealing has been used to select component values, but the approach is being extended to topology selection. (6 pages)High-level design of analogue circuitry using an analogue hardware description language
http://dl-live.theiet.org/content/conferences/10.1049/ic_19971118
A number of Analogue Hardware Description Languages (AHDL's) are now available; however experienced analogue designers appear to be apprehensive about their commercial exploitation as a design tool. This paper introduces the Design Assistant (DA), a high-level top down analogue design methodology that utilises an AHDL, SpectreHDL. Secondly the paper explores the design abstraction levels in the digital domain presenting suitable analogue counterparts. Furthermore, traditional high-level analogue design is compared with the DA behavioural-level, specifically comparing mathematical results with those generated from an AHDL. Finally the design of an IF transceiver is used to demonstrate the use of AHDL modelling provides benefits over traditional mathematical techniques. More specifically AHDL modelling provides greater detail during the simulation of the transceiver design and is also suited to system-level modelling. (8 pages)Analogue fault simulation - the nightmare
http://dl-live.theiet.org/content/conferences/10.1049/ic_19951206
Purely functional testing of modern analogue and mixed-signal ICs is becoming less acceptable as quality levels increase and shorter test times are required. The structural approach uses Analogue Fault Simulation to give an indication of fault coverage. No standard fault models or modelling tools exist for faulty devices, so fault models are usually developed using fault-free simulator device models which can be a poor approximation. Existing circuit simulators are thus poor at simulating faulty devices. Another drawback to AFS is the lengthy simulation time required. Behavioural level modelling can be used to address this issue, but there are some limitations associated with this. (6 pages)Advanced modeling techniques for subthreshold and full chip simulation
http://dl-live.theiet.org/content/conferences/10.1049/ic_19951208
For over 20 years, Berkeley SPICE and SPICE-like programs have been the standards for use in electrical circuit simulation. Over time, however, circuit simulation demands have changed and as a result, simulation techniques must change, as well. SPICE was originally designed to simulate circuits with device counts of order 100, while today designers would like to simulate circuits with hundreds of thousands of devices. In addition, the character of analog circuits is changing, as many designers want to operate transistors in subthreshold, in an effort to minimize power dissipation. In order to meet the accuracy demands of subthreshold designers, new transistor models, such as the Maher-Mead model available in Tanner Research's T-Spice simulator, have been developed. These transistor models match the physical device behavior much better than the standard SPICE transistor models. But accuracy comes at the expense of speed. In order to allow fast simulation with these state-of-the-art models, table techniques can be used to store computed model values so that the total number of model evaluations is kept low. These table techniques are useful not only to the analog subthreshold designer, but also to the digital designer, as using these techniques allows the simulation of very large circuits, even full chips. (3 pages)Neural networks implementation with VLSI
http://dl-live.theiet.org/content/conferences/10.1049/cp_19950605
This paper presents the design of a new and efficient winner-take-all (WTA) cell for the self-organising mapping (SOM) neuron. This cell is implemented in VLSI that provides both faster operation and a reduction in the number of transistors per cell compared to existing designs. The operation of the circuit is described and results of SPICE simulations are presented.A compact analogue radial basis function circuit
http://dl-live.theiet.org/content/conferences/10.1049/cp_19950602
We describe an analogue VLSI circuit which implements the radial basis function (RBF) algorithm, based around a compact Euclidean Distance calculator. A prototype chip has been fabricated and tested. First, we describe the RBF architecture and present results from the test chip. We then discuss the impact of device variations, which traditionally cause problems for analogue systems. Finally, we discuss the scaling of our results from the small test chip to a full-sized RBF system.Implementation issues for on-chip learning with analogue VLSI MLPS
http://dl-live.theiet.org/content/conferences/10.1049/cp_19950601
Microelectronic neural network technology has become sufficiently mature over the past few years that reliable performance can now be obtained from VLSI circuits under carefully controlled conditions. The use of analogue VLSI allows low power, low cost and area efficient hardware realisations which can perform the computationally intensive feed-forward operation of neural networks at high speed. These factors, coupled with the ability to interface directly with the analogue world, make real-time applications a possibility. This paper attempts to address some of the issues concerning in-situ learning with analogue VLSI multilayer perceptron (MLP) networks. We consider the modes used to train analogue neural networks, study weight storage and circuit precision issues, and identify the most promising training algorithms. We then make some conclusions based on results from analogue VLSI chips that we have designed, built and successfully tested.DYMPLES - an analogue current mode pulsed synapse
http://dl-live.theiet.org/content/conferences/10.1049/cp_19950603
Several artificial neural network (ANN) implementations require two-quadrant multiplications for neural state computations. Almost all previous analogue hardware implementations of two-quadrant multipliers for ANNs have used circuits operating in voltage mode. In the paper a chip consisting of synapses using current mode principles is presented. By basing the multiplier circuits on dynamic current mirrors, the aspirations were to produce synapse arrays that were easy to set up, were robust and cascadable and that also possessed better process tolerance than previous voltage mode devices. The hardware results presented from the Dynamic Mirror Pulsed Experimental Synapse (DYMPLES) chip are extremely encouraging, fulfilling all initial aspirations and showing that the synapse design does indeed possess the potential for process tolerance.Analogue IC Design: The Current-Mode Approach
http://dl-live.theiet.org/content/books/cs/pbcs002e
<p xmlns="http://pub2web.metastore.ingenta.com/ns/">Analogue IC Design has become the essential title covering the current-mode approach to integrated circuit design. The approach has sparked much interest in analogue electronics and is linked to important advances in integratedcircuit technology, such as CMOS VLSI which allows mixed analogue and digital circuits and high-speed GaAs processing.</p>Programmable analogue circuits with multilevel memristive device
http://dl-live.theiet.org/content/journals/10.1049/el.2012.3179
It is demonstrated that a nanoscale multilevel memristive device using titanium oxide can be used to form programmable analogue circuits without an active transistor. A multilevel memristive device enables a high a degree of programmability particularly for analogue applications since it will not introduce any significant parasitic components. Also, the ring oscillator application with the memristive device is merely a demonstrative example of the enabled high programmability.Charge compensation technique for switched-capacitor circuits
http://dl-live.theiet.org/content/journals/10.1049/el.2012.1340
A charge compensation technique is proposed for switched-capacitor S/H circuits and integrators. The compensated stages achieve better linearity with low power and relaxed sampling noise specifications. Analysis and simulations show that high linearity can be achieved, even while consuming low power.Analysis, design and control of zero-voltage switching quasi-resonant-positive output super lift Luo converter
http://dl-live.theiet.org/content/journals/10.1049/iet-pel.2009.0122
This study presents the analysis, design and voltage regulation of a zero-voltage switching quasi-resonant-positive output super lift Luo converter with low switching losses for industrial applications requiring regulated output voltage. To increase the power packing density, a simple control method using an analogue resonant controller UC3861 is used to regulate the output voltage against load variation and supply disturbance. The performance of the controller is verified by developing a prototype model of the converter and experimental results are presented. The results reveal the superiority of using a single dedicated IC for voltage regulation. Also it is observed that the converter provides maximum efficiency of 95% at full load.Quantitative method for evaluating quality of analogue VLSI layout
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_20000775
A quantitative benchmarking metric is presented for the evaluation of the quality of analogue layout. It facilitates comparisons between alternative design automation tools and, for a given tool, provides assessment of each layout instance. The quality metric reflects two principal concerns in layout design: area efficiency and net routing optimality. The algorithm has been developed to accommodate hierarchical structures, as well as flat designs. The metric allows the designer to alter the relative importance of area and routing efficiencies, although a recommendation is given on the appropriate balance. The results demonstrate the use of the metric to evaluate an automatic layout tool, and its effectiveness in providing a characterisation that corresponds to the expert designer's judgement.Automatic analogue circuit synthesis using genetic algorithms
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_20000770
Most analogue systems are designed manually because automatic circuit synthesis tools are available for only a limited range of design problems. A new approach to circuit synthesis based on genetic algorithms is presented. Using this method it is possible in principle to synthesise circuits to meet any linear or nonlinear, frequency-domain or time-domain, specification. When applied to existing filter design problems this circuit synthesis method produces design solutions that are more efficient than those resulting from formal design methods or created manually by an experienced analogue circuit designer.Non-Gaussian kernel circuits in analogue VLSI: implications for RBF network performance
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19990440
The authors present a cascadable circuit for the distance metric and nonlinear functions required by radial basis function (RBF) neural networks. The distance metric is a quadratic approximation to the Euclidean distance between two voltages, and the nonlinearity is produced using two MOS transistors. This circuit has been developed for pulse stream neural systems. The operation of the circuit is described and suggestions are made for its practical implementation in pulsed analogue VLSI. Since the nonlinearity generated by the circuit has not been used in RBFs before, software results are presented to demonstrate that the circuit can produce good classification performance. However, software simulations show that the shape of the nonlinearity has implications for the performance of RBFs using the circuit. The authors consider the implications of these results to the development of pulsed analogue RBF chips in the limited precision environment of analogue VLSI. Based on their findings, they make suggestions for the shape and range of future centre circuits to make them robust to this limited precision and which they believe will help ensure good classification performance is obtained in hardware.Field programmable analogue array implementation of fractional step filters
http://dl-live.theiet.org/content/journals/10.1049/iet-cds.2010.0141
In this study, the authors propose the use of field programmable analogue array hardware to implement an approximated fractional step transfer function of order (<i xmlns="http://pub2web.metastore.ingenta.com/ns/">n</i>+α) where <i xmlns="http://pub2web.metastore.ingenta.com/ns/">n</i> is an integer and 0 < α < 1. The authors show how these filters can be designed using an integer order transfer function approximation of the fractional order Laplacian operator <i xmlns="http://pub2web.metastore.ingenta.com/ns/">s</i><sup xmlns="http://pub2web.metastore.ingenta.com/ns/">α</sup>. First and fourth-order low- and high-pass filters with fractional steps from 0.1 to 0.9, that is of order 1.1–1.9 and 4.1–4.9, respectively, are given as examples. MATLAB simulations and experimental results of the filters verify the implementation and operation of the fractional step filters.Novel analogue CMOS defuzzification circuit
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19951927
An analogue CMOS circuit technique for the implementation of defuzzification is proposed. The defuzzification method is based upon the normalisation locked loop (NLL) method, but with two key improvements: the compact representation of triangular membership functions, and a mechanism to ensure that the relative rule weight proportions are preserved during normalisation. Circuit complexity is considerably reduced by combining these two operations in a single circuit stage. The proposed weight circuit, which evaluates normalised rule weights, has been realised using current squaring circuits proposed by Bult and Wallinga (1987). The weight circuit has been fabricated in a 2.0 µm CMOS process. Results obtained from the fabricated circuit operating as part of a NLL are presented.Current-mode defuzzifier circuit to realise the centroid strategy
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19971378
A current-mode circuit based on the square-rooter/multiplier and squarer/divider circuits to realise the centre-of-gravity defuzzification strategy is described. The current-mode approach allows it to operate at 3.3 V without degrading its dynamic range. The proposed circuit was fabricated in 0.8 µm single-polysilicon–double-metal technology, and the experimental results showed that it can operate at high speed with low power dissipation.Estimation of statistical variables for analogue fault detectability evaluation
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19990581
An efficient method for estimating the mean value and standard deviation of output measurements is introduced. It takes into account statistical variations of component values and gives accurate and realistic results with less computational time compared with the Monte Carlo technique. A method for the estimation of fault detectability of output measurements in a simulation-before-test approach is proposed. Results from four different circuits show the effectiveness of the methods in selecting the measurement with the highest detectability among a given set and also their application for input stimulus selection.Collective process circuit that sorts
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19971148
Comparing and sorting are common functions in natural and artificial systems. Many known algorithms that sort <i xmlns="http://pub2web.metastore.ingenta.com/ns/">m</i> numbers require time from <i xmlns="http://pub2web.metastore.ingenta.com/ns/">O</i>(<i xmlns="http://pub2web.metastore.ingenta.com/ns/">m</i><sup xmlns="http://pub2web.metastore.ingenta.com/ns/">2</sup>) to <i xmlns="http://pub2web.metastore.ingenta.com/ns/">O</i>(<i xmlns="http://pub2web.metastore.ingenta.com/ns/">m</i>). Algorithms to find the greatest number have been realised in neural networks and discrete time systems. Presented in the paper is a new circuit, the MAXOR, which incorporates a continuous time recursive collective process for finding the maximum of many inputs and sort inputs, like the <i xmlns="http://pub2web.metastore.ingenta.com/ns/">O</i>(<i xmlns="http://pub2web.metastore.ingenta.com/ns/">m</i>) spaghetti sort algorithm, when furnished with synchronous control. The resulting output is broadcast throughout the process. The precision η required of the circuit is only that needed to distinguish between the maximum and next lower inputs. Stability is assured within practical parameters where the output is observed to settle in linearised time <i xmlns="http://pub2web.metastore.ingenta.com/ns/">O</i>(<i xmlns="http://pub2web.metastore.ingenta.com/ns/">m</i>/η).Minimal-connectivity circuit for analogue sorting
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19990323
A CMOS circuit for sorting analogue current-mode quantities is presented. The highly modular architecture integrates several elementary cells operating at the local level. The VLSI-oriented approach minimises wiring and silicon area, because very few devices are involved. The sorting process is completed in <i xmlns="http://pub2web.metastore.ingenta.com/ns/">O</i>(<i xmlns="http://pub2web.metastore.ingenta.com/ns/">n</i>) time. Simulations at the VLSI layout level prove the effectiveness of the approach in neural-network training applications.CAD tools for embedded analogue circuits in mixed-signal integrated systems on chip
http://dl-live.theiet.org/content/journals/10.1049/ip-cdt_20045116
The paper gives an overview of methods and tools that are needed to design and embed analogue and RF blocks in mixed-signal integrated systems on chip (SoC). The design of these SoCs is characterised by growing design complexities and shortening time to market constraints. This requires new mixed-signal design methodologies and flows, including high-level architectural explorations and techniques for analogue behavioural modelling. This also calls for new methods to increase analogue design productivity, such as the reuse of analogue blocks as well as the adoption of analogue and RF circuit and layout synthesis tools. Also, more detailed modelling and verification tools are needed that can analyse signal integrity and crosstalk problems, especially noise coupling problems caused by the embedding of the analogue circuits in a digital environment. Solutions that already exist today are presented, and challenges that still remain to be solved are outlined.Generation of optimised fault lists for simulation of analogue circuits and test programs
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19990691
The definition of a universally acceptable analogue fault model has been a major obstacle to the acceptance, by industry, of any of the new test and testability techniques that have been proposed for analogue and mixed-signal circuits. This is largely because analogue faults are difficult to model and very time consuming to simulate. Previous independent research has demonstrated how inductive fault analysis can be used to reduce the size of a fault set and how circuit sensitivity analysis can be employed to ascertain what constitutes a fault for each circuit component. The authors combine these two principles by first employing an inductive fault analysis to eliminate faults which are unlikely to occur from the fault set, and then employing a circuit sensitivity analysis to eliminate from the remaining set ‘faults’ which have no effect on circuit functionality. As a result, fault simulation becomes a significantly less onerous task and the evaluation and comparison of test programs and techniques can be achieved much more conveniently.Analogue VLSI Morris-Lecar neuron
http://dl-live.theiet.org/content/journals/10.1049/el_19970686
The authors have developed a silicon neuron that exhibits properties similar to those of the Morris-Lecar neuron. The Morris-Lecar model is a two-state mathematical model that possesses physiological properties similar to those of actual neurons. The circuit behaviour is analysed, based on the geometry of nullclines in state space and analytical results are compared with experimental data for a circuit implemented in a 2 µm <i xmlns="http://pub2web.metastore.ingenta.com/ns/">n</i>-well process.Current-mode fully-programmable piece-wise-linear block for neuro-fuzzy applications
http://dl-live.theiet.org/content/journals/10.1049/el_20020831
A new method to implement an arbitrary piece-wise-linear characteristic in current mode is presented. Each of the breaking points and each slope is separately controllable. As an example a block that implements an N-shaped piece-wise-linearity has been designed. The N-shaped block operates in the subthreshold region and uses only ten transistors. These characteristics make it especially suitable for large arrays of neuro-fuzzy systems where the number of transistors and power consumption per cell is an important concern. A prototype of this block has been fabricated in a 0.35 µm CMOS technology. The functionality and programmability of this circuit has been verified through experimental results.Analogue CMOS high-frequency continuous wavelet transform circuit
http://dl-live.theiet.org/content/journals/10.1049/el_19990077
A 16-channel analogue CMOS high-frequency continuous wavelet transform circuit has been realised. The circuit performs a time-frequency decomposition of a high-frequency input signal. A 100 MHz operating frequency, 45 MHz bandwidth, and 40 mW/channel power dissipation have been achieved using a 0.5 µm CMOS process.Analogue integrated-circuit design for sustained neurons in a fly
http://dl-live.theiet.org/content/journals/10.1049/el_20010631
An analogue integrated-circuit design of a fly's sustained neurons is presented. Circuit simulation of the design shows that the output exhibits non-associative learning in agreement with electrophysiological studies of these neurons. The output is shown to encode the contrast of the input.Simple and accurate voltage adder/subtractor
http://dl-live.theiet.org/content/journals/10.1049/el_19970667
A low-power analogue voltage adder/subtractor is presented. It is based on the exponential characteristic of MOST when biased in weak inversion, and uses the bulk as an active terminal. <1% error is achieved over a 440 mV input range.Capacitor-free leaky integrator for biomimic artificial neurons
http://dl-live.theiet.org/content/journals/10.1049/el_20020679
A method for implementing capacitor-free leaky integrators for biomimic artificial neurons is presented. The method employs a low-gain non-inverting amplifier with nonlinear feedback resistors implemented from PMOS devices operating in the triode region.Simple low power analogue MOS voltage adder
http://dl-live.theiet.org/content/journals/10.1049/el_19990414
A simple, low power, NMOS analogue voltage adder, suitable for VLSIC implementation is presented. It is based on the inherent square law of MOS transistors operating in saturation mode. Using a 3.3 V source, the circuit's input voltage range is ±3 V, with an error less than 0.3% compared with the ideal sum of the inputs. The power consumption is < 0.5 mW and THD < –36 dB for the full range of operation.Low-voltage CMOS four-quadrant analogue multiplier for RF applications
http://dl-live.theiet.org/content/journals/10.1049/el_19981632
A CMOS four-quadrant multiplier consisting of four MOS transistors operating in the saturation region is introduced. The circuit exploits the quadratic relation between the current and voltage of the MOS transistor in saturation. Simulation results show that, for a supply voltage of 1.2 V, multiplication can be performed at a frequency of 1.8 GHz, achieving better performances than a recently proposed similar architecture.Architectural synthesis of high-level analogue VHDL-AMS descriptions using netlist extraction from parse trees
http://dl-live.theiet.org/content/journals/10.1049/el_20001202
A technique of translating high-level analogue dynamic system behavioural models from VHDL-AMS parse trees into circuit-level netlists is described. The primary application of this work is automatic synthesis of general analogue dynamic systems with feedback. The technique is demonstrated with a practical example of Lorenz's chaos system synthesis.Digitally programmable nonlinear function generator for neural networks
http://dl-live.theiet.org/content/journals/10.1049/el_20056397
The design of a new digitally programmable analogue circuit well suited for the implementation of several sets of nonlinear functions by approximating them by using a linear combination of sigmoidal terms is presented. The proposed circuit, allowing the building of several collections of nonlinear functions, would be useful in modelling artificial neural networks, fuzzy as well as partial differential equations based circuits.Programmable spatial processing imager chip
http://dl-live.theiet.org/content/journals/10.1049/el_20010455
The authors present an architectural overview and results from an image processor chip for realising steerable spatial filtering at the focal plane. Convolutions of the image with multiple programmable kernels are realised with area-efficient, real-time circuits. In addition to the raw intensity image, the chip outputs four processed images in parallel. The convolutions are implemented with digitally programmable analogue processors. The chip performs 5.7 GOPS/mW while outputting four processed images in parallel.Analogue median/average image filter based on cellular neural network paradigm
http://dl-live.theiet.org/content/journals/10.1049/el_19991091
A cellular neural network-based image filter is presented, which allows for median and mean image filtering. The circuit implements an array of 3 × 64 analogue processing elements (cells) and appropriate additional circuitry. Images are loaded into the circuit, are read out of the circuit serially, and are processed in real-time.Settling optimised sample-and-hold circuit with high-linearity input switch in 65 nm CMOS
http://dl-live.theiet.org/content/journals/10.1049/el.2010.8724
A settling optimised sample-and-hold (SH) circuit with a wideband high-linearity input switch is presented. A proposed input switch with floating-well isolation achieves low on-resistance and high-linearity through a wide input frequency range. A method for the SH to acquire the optimised settling behaviour by choosing a feedback switch with suitable on-resistance is proposed to achieve low-power target. Simulation results show that the performance of the SH is improved considerably.CNN cell for computing disparity map
http://dl-live.theiet.org/content/journals/10.1049/el_20010457
The real-time estimation of the distance of objects from an observer is a critical issue in several application fields. A new cellular neural network circuit that uses a stereo vision algorithm to compute the disparity map is presented.SPICE-compatible modelling technique for simulating floating-gate transistors
http://dl-live.theiet.org/content/journals/10.1049/el.2011.0458
A technique is introduced to enable the simulation of floating-gate transistors within standard analogue circuit simulators, such as SPICE. This technique can be used in all types of circuit simulations, ranging from DC sweeps to charge-modification scenarios. The technique is then used to simulate several analogue circuits, the results of which show strong agreement with identical circuits fabricated in standard CMOS processes.Analysis and synthesis of double-layer MOSFET networks for smart sensory systems
http://dl-live.theiet.org/content/journals/10.1049/el_19981413
An analysis method to find the natural response of double-layer planar lattice networks is found and its stability discussed. Following the proposed approach, a new circuit able to perform feature extraction at the sensory level by means of a convolution with a Gabor-like kernel is synthesised. The circuit, based on MOS transistors working in the subthreshold region, has been simulated and successfully compared with theoretical expectations. Its main features are the compactness, low-power and full programmability of the convolutional kernel.Analogue squarer and multiplier based on floating-gate MOS transistors
http://dl-live.theiet.org/content/journals/10.1049/el_19980639
A simple squarer based on floating-gate MOS transistors is presented. The squarer has rail-to-rail input range with less than 0.5% non-linearity error. Using this squarer single-ended and/or differential signals can be processed without additional circuitry. Also, a four quadrant analogue multiplier can be realised using the proposed squarer. Simulation results are given to verify the theoretical analysis.Implementation of adaptable and hierarchical fuzzy T-norm
http://dl-live.theiet.org/content/journals/10.1049/el_19991415
A new configurable multiple-input fuzzy T-norm circuit is proposed, based on a monotonically decreasing function for the construction of the T-norm. The operator can dynamically adapt its behaviour (i.e. its behaviour can lie between the minimum, the product, or other parametric operators), and allows the use of hierarchical variables and rules.Programmable current-mode neural network for implementation in analogue MOS VLSI
http://dl-live.theiet.org/content/journals/10.1049/ip-g-2.1990.0027
This paper presents simple and efficient circuit techniques for the implementation of feedback and feedforward neural networks in analogue MOS VLSI. Synaptic weight storage is achieved using programmable threshold-voltage devices, such as the metal-nitride-semiconductor (MNOS) transistor and the floating-gate MOS (FGMOS) transistor. Basic electronic neural functions, such as adaptive weighted summation and sigmoidal nonlinearity functions, are implemented using simple current-mode analogue signal processing building blocks. This is particularly attractive when neural networks of increased complexity are implemented in modern scaled VLSI technologies, where voltage signal handling is severely limited for analogue applications. A four-neuron chip is designed, using the new current-mode building blocks, fabricated and experimentally verified using the MOSIS 2μm double-poly, double-metal <i xmlns="http://pub2web.metastore.ingenta.com/ns/">p</i>-well CMOS process. Intensive computer simulation and experimental results are provided.Analogue adaptive neural network circuit
http://dl-live.theiet.org/content/journals/10.1049/ip-g-2.1991.0117
Current integrated circuits realising neural networks take up too much area for implementing synapses. The paper presents a one-transistor (IT) synapse circuit that uses a single MOS transistor, which is more efficient for VLSI implementation of adaptive neural networks, compared to other synapse circuits. This 1T synapse circuit can be used to implement multiply/divide/sum circuits to realise an adaptive neural network. The feasibility of using this circuit in adaptive neural networks is demonstrated by a 4-bit analogue-to-digital converter circuit, based on the Hopfield modified neural network model, with an analogue LMS adaptive feedback. DC and transient studies show that 1T synapse circuits with an analogue adaptive feedback circuit can be used more efficiently for VLSI implementation of adaptive neural networks.Design of an analogue subthreshold multiplier suitable for implementing an artificial neural network
http://dl-live.theiet.org/content/journals/10.1049/ip-g-2.1992.0044
The paper describes work undertaken as a final-year undergraduate project and considers the design of an analogue VLSI implementation of the multi-layer perceptron artificial neural network. The network is principally composed of multipliers, and therefore the design effort concentrated on the development of a spaceefficient multiplier. The circuit exploits the subthreshold region of operation of a MOSFET and it was necessary to examine in detail the modelling of this region of operation. In the course of the work, design tools made available under the ECAD initiative were used; in particular, the circuit simulator HSPICE was used for parameter extraction, in an unconventional way, to great advantage.Hebbian plasticity in mos synapses
http://dl-live.theiet.org/content/journals/10.1049/ip-f-2.1991.0003
Hebbian learning in analogue CMOS synapses is obtained by using the transistor characteristics to approximate the multiplicative correlation of neural signals. <i xmlns="http://pub2web.metastore.ingenta.com/ns/">In situ</i> analogue learning is employed, which means that computations of synaptic weight changes occur continuously during the normal operation of the artificial neural network. The transistor complexity of a synapse is minimised by departing from strict adherence to classical multiplicative rules; learning remains consistent, however, with the original qualitative statement of Hebb. Simulations of circuits with three transistors per synapse in the case of unipolar weights suggest that appropriate learning and forgetting behaviour is obtained at the synaptic level by adopting these area-efficient MOS learning rules in lieu of classical analytical formulations. The theory at the systems level corresponding to these learning rules has not yet been developed.