New Publications are available for Semiconductor technology
http://dl-live.theiet.org
New Publications are available now online for this publication.
Please follow the links to view the publication.Semiconductors + software: the fuel of the modern economy (Abstract only)
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.1867
Summary form only given. Since the birth of the transistor in 1947 semiconductor technology has seen a rapid rate of development, leading to a vast diversity of applications. Today's integrated circuits can now contain up to a billion transistors and provide the fuel for the Digital Information Age which so seamlessly affects all of our lives and touches billions of people on our planet. Today's technology is "embedded" or hidden in applications such as mobile phones, digital cameras, information appliances, control systems, automotive electronics with the digital systems of today doing the work of mechanical systems of the past. The software content of many systems is now more costly than the metal out of which they are built. With the opposing forces of added complexity with increasing pressure to shorten time to market, the semiconductor industry has reached a level of maturity that has caused horizontal specialist companies to emerge with a theme of global teamwork being necessary for success. Sir Robin Saxby will give a brief history of the semiconductor industry, highlighting the new challenges and applications as we look toward 2020. He will touch on the way in which our power networks have embraced the advancement of control systems in power distribution. He will also discuss how developments in this field have given rise to more powerful yet more power efficient and lower cost devices. (1 page)How silicon will transform healthcare
http://dl-live.theiet.org/content/conferences/10.1049/ic.2007.1686
Presented is a series of slides of the author's presentation.Fabrication of GaAs Devices
http://dl-live.theiet.org/content/books/cs/pbep006e
<p xmlns="http://pub2web.metastore.ingenta.com/ns/">This book provides fundamental and practical information on all aspects of GaAs processing. The book also gives pragmatic advice on cleaning and passivation, wet and dry etching and photolithography, and dry etching.</p>Silicon Wafer Bonding Technology for VLSI and MEMS Applications
http://dl-live.theiet.org/content/books/cs/pbep001e
<p xmlns="http://pub2web.metastore.ingenta.com/ns/">The use of silicon-on-insulator (SOI) technology in microelectronics is proliferating and is ready to be applied in a growing number of IC fabrication situations. Bonding of single crystal Si to dielectrics, normally silicon dioxide, is a key method of producing SOI structures and this book is designed to directly assist engineers in applying emerging SOI technology in practice.</p>Process Technology for Silicon Carbide Devices
http://dl-live.theiet.org/content/books/cs/pbep002e
<p xmlns="http://pub2web.metastore.ingenta.com/ns/">This book explains why SiC is so useful in electronics, gives clear guidance on the various processing steps (growth, doping, etching, contact formation, dielectrics etc) and describes how these are integrated in device manufacture. The book should serve as an advanced tutorial and reference for those involved in applying the very latest technology emerging from university and commercial laboratories around the world.</p>Prototype thyratron replacement using semiconductors [pulsed power switch]
http://dl-live.theiet.org/content/conferences/10.1049/ic_20010137
Thyratrons have been used for many years for applications that require fast switching of high voltage, high current pulses. They are traditionally employed with a PFN with typically short pulse widths (1 to 100 μS). Recent advances in semiconductor technology now make it possible to build a solid state alternative to the thyratron. Semiconductor switches are particularly suitable for applications that require longer pulse widths and higher average powers because or their very low conduction losses. This paper describes a prototype solid state assembly that has electrical performance comparable with high power thyratrons. (4 pages)Europractice - microsystems activities in Framework 5
http://dl-live.theiet.org/content/conferences/10.1049/ic_20000189
Reduces the barriers to entry for users: access to information; lower cost prototyping; and first user software licences. Improves the supply of skilled technical staff: Euro-training courses for industry; technology transfer from institutes; and university graduates with project experience. Increases awareness of technology and its benefits; publicity for case studies; and techno-economic training courses. Access to funding involves business plan preparation support. (10 pages)Advances in PV semiconductor materials and technology
http://dl-live.theiet.org/content/conferences/10.1049/ic_19970363
It is now accepted that photovoltaics is the most promising of the renewable energy sources for electric power generation. Photovoltaic's ability to provide reliable, high grade energy over an extended lifetime is now well proven in both space and terrestrial applications. Widespread adoption of this clean, silent power source, however, still awaits the achievement of a number of outstanding technical and economic objectives. Extensive research into photovoltaic technology over the last two decades has done enough to conclude that all these goals can be met. The present challenge is to apply these results industrially and commercially so as to make the dream and reality. Photovoltaics can only provide an efficient service to its users if it provides a transparent and trouble free source of electricity. This involves the application of photovoltaic devices in well integrated systems which also include appropriate mechanical and electrical interfaces. The author focuses on one part of the system-the photovoltaic generator itself. This paper reviews the status of international developments and the contributions which they can make in achieving this objective. (4 pages)The future of on-chip terahertz metal-pipe rectangular waveguides implemented using micromachining and multilayer technologies
http://dl-live.theiet.org/content/conferences/10.1049/ic_19970840
Existing terahertz integrated circuit technologies rely heavily on slotline, coplanar strip and coplanar waveguide transmission line components which exhibit extremely low Q-factors and poor line-to-line isolation. To overcome these shortcomings, at both mm-wave and sub-mm-wave frequencies, universities in the US have been developing ultra-high performance micromachined guided-wave structures, in the form of membrane supported quasi-TEM lines and metal-pipe rectangular waveguides. At the same time, Japanese industry has been making great strides in the development of multilayer 3D MMIC structures for applications at lower frequencies. Within the framework of these activities, this paper compares and contrasts micromachining and multilayer technologies for implementing on-chip metal-pipe rectangular waveguides for terahertz applications. The achievements reported so far are reviewed and the current developments being made within the UK are discussed. (10 pages)Monolithic integration in InGaAs/InGaAsP multiple quantum well structures using laser and plasma processing
http://dl-live.theiet.org/content/conferences/10.1049/ic_19971239
Precise control over local optical and electrical characteristics across a semiconductor wafer is of fundamental importance for fabrication of photonic integrated circuits (PICs). Here we report the use of two basic quantum well intermixing (QWI) techniques, laser processing and plasma processing induced disordering. Extended cavity ridge lasers were fabricated using both techniques. The light-current (L-I) characteristics of lasers with and without extended passive waveguides were measured, and it was shown that threshold current has only a slight increase for the extended cavity lasers with 1 mm extended cavity compared to the lasers with no extended cavity. The losses in the passive section of the extended cavity lasers are calculated. (5 pages)Multiwavelength DFB-LD array module using self-aligned solder bump bonding
http://dl-live.theiet.org/content/conferences/10.1049/cp_19971454
Eight-wavelength 1.55-μm DFB-LD array modules with 1.6-nm wavelength spacing have been made by self-aligned assembly using a stripe-type solder bump flip-chip bonding, and the fiber output optical power for each channel was greater than ~20 dBm. These modules are attractive low-cost multiwavelength light sources for use in WDM systems.Thin film piezoelectric layers for sensing and actuation in microstructures
http://dl-live.theiet.org/content/conferences/10.1049/ic_19961220
Silicon micromachined sensors and actuators that incorporate piezoelectric materials are considered. Widespread application has been restricted by the properties of the materials available. The prospects for micromachined piezoelectric devices have improved since it became possible to deposit PbZr<sub xmlns="http://pub2web.metastore.ingenta.com/ns/">x</sub>Ti<sub xmlns="http://pub2web.metastore.ingenta.com/ns/">1-x</sub>O<sub xmlns="http://pub2web.metastore.ingenta.com/ns/">3</sub> layers over large areas with goad uniformity and reproducibility. Considerable progress has been made in developing process technologies for integrating PbZr<sub xmlns="http://pub2web.metastore.ingenta.com/ns/">x</sub>Ti<sub xmlns="http://pub2web.metastore.ingenta.com/ns/">1-x</sub>O<sub xmlns="http://pub2web.metastore.ingenta.com/ns/">3</sub> thin films layers with surface and bulk micromachined structures. As incorporation of these materials in silicon microstructures becomes established it will be possible to consider the integration of bipolar and CMOS electronics with the sensors and actuators. Material and process integration techniques developed to incorporate thin film PbZr<sub xmlns="http://pub2web.metastore.ingenta.com/ns/">x</sub>Ti<sub xmlns="http://pub2web.metastore.ingenta.com/ns/">1-x</sub>O<sub xmlns="http://pub2web.metastore.ingenta.com/ns/">3</sub> onto bulk micromachined structures are described. The design of a triaxial accelerometer and the processing steps required are outlined. (1 page)Processing and modelling of micromachined cantilever valves
http://dl-live.theiet.org/content/conferences/10.1049/ic_19961017
We have fabricated and simulated micromachined cantilever valves. For processing, bulk micromachining and silicon fusion bonding of a duct-containing-wafer and a flap-containing-wafer are used. After the release of the cantilever with buffered HF a rinse in toluene avoids sticking. Measurements revealed a good forward to reverse flow rate ratio, where leakage rates were below 1 μl min<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">-1</sup>. Static simulations were done by coupling mechanical (ANSYS) and fluidic (FLOWSD) simulators. The modelling results were in good agreement with measured results and give confidence in this simulator. Dynamic simulations were realized with an impact model of the cantilever sitting on top of the duct. A lumped system was used together with measured results of the resonance frequency and the quality factor of a cantilever in water. (3 pages)Silicon-on-insulator material for sensors and accelerometers
http://dl-live.theiet.org/content/conferences/10.1049/ic_19961221
Using commercially available silicon on insulator (SOI) starting material gives the opportunity for a manufacturable acceleration sensor fabricated using a single wafer process. A focused ion beam (FIB) is used to cut a Si cantilever at an oblique angle to form the gap in the structure. This overall process sequence is simple and for high-value sensors it is not a serious disadvantage to use the serial FIB process to cut the beams. The general approach of using bonded silicon-on-insulator wafers for machining single crystal Si micromechanical structures is simple, flexible and has many possible applications in sensors and MEMS. (5 pages)A silicon membrane gyroscope with electrostatic actuation
http://dl-live.theiet.org/content/conferences/10.1049/ic_19961217
Vibrating gyroscopes employing matched primary and secondary natural modes of vibration offer high sensitivities to applied rates of turn. The preferred approach to matching the two modes is, to base the design of the gyroscope on a symmetrical structure which can be fabricated without the need to achieve dimensional accuracy. In the membrane gyroscope, the symmetry of the membrane/inertial pyramidal mass results from the anisotropic bulk etching of silicon with EDP. The primary mode of vibration with angular velocity ω<sub xmlns="http://pub2web.metastore.ingenta.com/ns/">p</sub> is shown. Since the primary motion is at resonance large amplitudes of vibration, i.e. angular velocity, can be achieved with little drive force. The presence of a rate of turn exerts a Coriolis force on the structure which is proportional to the product of the angular velocity of the primary motion and the applied rate of turn. This force excites the secondary mode into vibration with an angular velocity ω<sub xmlns="http://pub2web.metastore.ingenta.com/ns/">s</sub> that is a measure of the rate of turn. (7 pages)Prospects for terahertz technology
http://dl-live.theiet.org/content/conferences/10.1049/ic_19951441
The interest in wireless local area networks has stimulated considerable research activity at frequencies above 60 GHz. Indeed the idea of exploring the potential bandwidth and propagation properties for carriers in the range 100 GHz to 1 THz has led to increased investment in terahertz technology research. There are now worldwide initiatives across the terahertz frequency range (60 GHz to 10 THz). This activity has prompted a shift in emphasis from detection of terahertz signals (primarily the domain of radio astronomy) to the generation of signals for local oscillators. Simultaneously, this reflects the fact that the biggest challenge facing the development of terahertz technology is the requirement for a solid-state RF sources with useful output power and efficiency, whilst maintaining an acceptable noise performance. This is an essential pre-requisite for the development of compact low power transmitters and receivers. In spite of these difficulties SIS receivers have been built at frequencies up to 600 GHz and oscillators based on semiconductor devices operating in the frequency range 100 to 300 GHz are now widely reported. The paper addresses the prospects for terahertz technology in the context of satisfying the requirements for future communication systems and considers circuits and devices suitable for operation in this frequency regime. It examines the state-of-the-art in semiconductor device technology for terahertz applications and the prospect of monolithic integrated circuit technology for frequencies above 100 GHz. (6 pages)Ultrafast transistors and ballistic devices
http://dl-live.theiet.org/content/conferences/10.1049/ic_19951490
This paper is concerned with the some of the details of the engineering of ultrafast transistors based on GaAs and InP for operation at and above 94 GHz. We illustrate some of the short-channel problems which arise in high-speed devices, discuss fabrication techniques for the critical gate region of the transistor, and report our most recent results on both substrates, including some of the first W-band on-wafer measurements made on such devices. We also describe a ballistic mixer device for possible application above 100 GHz, utilising a new intrinsically fast non-linear phenomenon for mixing and frequency conversion. (5 pages)Prospects for the exploitation of SiGe technologies
http://dl-live.theiet.org/content/conferences/10.1049/ic_19950177
We examine the prospects for the exploitation of SiGe technologies, paying particular attention to the element of competition provided by GaAs and by the continually improving level of performance expected of more conventional Si technologies. (4 pages)Electrical characterisations of new microgap surge absorber fabricated by using conventional semiconductor technology
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_20010248
The structure of the microgap and the manufacturing processes for a new type of microgap surge absorber, fabricated by semiconductor technology, are described. A very stable spark-over voltage with a narrow distribution was obtained by coating the metallic films in the microgap. As well as the desirable characteristics of common microgap surge absorbers, this new type of microgap surge absorber has other advantages such as small size, low cost and suitability for mass production.Three-dimensional integrated circuits implementation of multiple applications emphasising manufacture reuse
http://dl-live.theiet.org/content/journals/10.1049/iet-cdt.2009.0118
The authors propose a platform-based approach called Chipsburger for three-dimensional integrated circuits (3D IC) implementation of multiple electronics systems. The authors emphasise manufacturing reuse to lower the total non-recurring engineering and mass-production cost of 3D chips for multiple applications. Given a set of applications each employing a set of IPs and needing a certain amount of mass-production volume, the author's target 3D IC stack consists of platform dies and customised dies. Platform dies can be manufactured in large volume at low unit cost and used in multiple applications; Customised dies for individual application, on the other hand, will be smaller and easier to implement, as certain functionality has been allocated to the platform dies. The authors have developed a 3D IC cost model to evaluate platform-die configurations and compare the cost benefit of Chipsburger with that of either one 2D system-on-a-chip or 3D IC per application. The authors also develop a platform generator program for finding an optimised platform for a set of applications. Experimental results over industrial examples indicate that Chipsburger is indeed cost-effective for certain range of volume requirements.Thin film polycrystalline silicon solar cell on ceramics with a seeding layer formed via aluminium-induced crystallisation of amorphous silicon
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_20030630
Thin film polycrystalline silicon solar cells on foreign substrates are viewed as one of the most promising approaches to cost reduction in photovoltaics. To enhance the quality of the film, the use of ‘seeding layers’ prior to deposition of active material is being investigated. It has been shown that a phenomenon suitable to create such a seeding layer is the aluminium-induced crystallisation of amorphous silicon. Previous work mainly considered glass as the substrate of choice, thereby introducing limitations on the deposition temperature. Results concerning the application of such a technique to ceramic substrates (allowing the use of high-temperature CVD) are described. Also, the first reported results of a solar cell made in silicon deposited on these seeding layers are presented.Thin film silicon materials and solar cells grown by pulsed PECVD technique
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_20030627
Pulsed plasma enhanced chemical vapour deposition (PECVD) involves modulation of standard 13.56 MHz RF plasma in the kilohertz range. This allows an increase in the electron density during the ‘ON’ cycle, while in the ‘OFF’ cycle, neutralising the ions responsible for dust formation in the plasma. The authors report the development of state-of-the-art nanocrystalline Si (nc-Si:H) materials using a pulsed PECVD technique with 220 crystallite orientation, grain size of ∼200 Å, low O concentration and a minority carrier diffusion length <i xmlns="http://pub2web.metastore.ingenta.com/ns/">L</i><sub xmlns="http://pub2web.metastore.ingenta.com/ns/">d</sub> of ∼1.2 μm. The crucial effects of the p/i interface and the incubation layer have been investigated and an efficiency of ∼7.5% for a single junction nc-Si:H p-i-n device has been achieved for an i-layer thickness of 1.4 μm, using non-optimised textured substrates.Low-temperature Au/Si wafer bonding
http://dl-live.theiet.org/content/journals/10.1049/el.2010.1381
The non-uniformity and anisotropy of Au/Si reaction, which results in the formation of craters at the Au/Si bonding interface, are investigated. The non-uniformity of Au/Si reaction is due to the native oxide on the bare Si surface. A different interfacial morphology of Au/Si bonding is observed and explained by a proposed model. To achieve a uniform bonding interface, a Ti/Au layer is deposited onto the bare Si surface, in which the Ti layer is used to decompose the native oxide during bonding. By the proposed bonding structure, a uniform bonding interface without craters has been achieved.Development and characteristics of MOSFET protein chip using nano SAMs
http://dl-live.theiet.org/content/journals/10.1049/el_20040134
Generally, the drain current of a MOSFET is varied by the gate potential. As such, the drain current of a MOSFET protein chip can be varied by Ribosomal proteins that have a positive charge. These current variations can then be used as the response of the protein chip. The current variation in the proposed MOSFET protein chip was about 11.5% with a protein concentration of 0.5 mM.Framework for performing rapid evaluation of 3D SoCs
http://dl-live.theiet.org/content/journals/10.1049/el.2012.1321
Integrating more functionality in a smaller form factor with lower power consumption pushes traditional semiconductor technology scaling to its limits. Three-dimensional (3D) chip stacking is touted as the silver bullet technology that can keep Moore's momentum and fuel the next wave of consumer electronic products. Introduced is a framework that enables rapid evaluation of 3D SoCs with existing physical design tools.Si and SiC layer transfer by high temperature hydrogen implantation and lower temperature layer splitting
http://dl-live.theiet.org/content/journals/10.1049/el_19980295
High quality Si and SiC layers which were implanted by H at 400 and 800°C, respectively, were transferred onto an Si substrate and glass by wafer bonding and layer splitting at temperatures lower than the corresponding H-implantation temperatures.<i xmlns="http://pub2web.metastore.ingenta.com/ns/">p</i>-diamond/<i xmlns="http://pub2web.metastore.ingenta.com/ns/">n</i>-GaAs junctions formed by direct bonding
http://dl-live.theiet.org/content/journals/10.1049/el_19960018
The direct bonding of an <i xmlns="http://pub2web.metastore.ingenta.com/ns/">n</i>-GaAs thin film onto the surface of epitaxial <i xmlns="http://pub2web.metastore.ingenta.com/ns/">p</i>-diamond is demonstrated. A rectifying characteristic is obtained for the present <i xmlns="http://pub2web.metastore.ingenta.com/ns/">p</i>-diamond/<i xmlns="http://pub2web.metastore.ingenta.com/ns/">n</i>-GaAs bonded junction system. Moreover, the occurrence of the photovoltaic effect at the junction is observed under illumination by an AlGaAs laser operated at 789 nm. A diamond/GaAs <i xmlns="http://pub2web.metastore.ingenta.com/ns/">pn</i> junction can be formed by direct bonding.Backgating reduction in MESFETs using an AlAs native oxide buffer layer
http://dl-live.theiet.org/content/journals/10.1049/el_19961529
The authors present a new approach to the reduction of the backgating effect in GaAs MESFETs. A thin 1200 Å layer of the native oxide Al<i xmlns="http://pub2web.metastore.ingenta.com/ns/"><sub>x</sub></i>O<i xmlns="http://pub2web.metastore.ingenta.com/ns/"><sub>y</sub></i> is used in the buffer layer directly below the conducting channel and increases the backgating threshold to –17 V, while retaining excellent device characteristics.Improved LOCOS isolation for thin-film SOI MOSFETs
http://dl-live.theiet.org/content/journals/10.1049/el_19961210
The authors propose the use of a recessed LOCOS technique instead of a standard LOCOS process to eliminate parasitic edge transistor leakage in thin-film SOI MOSFETs. This technique helps to increase the sidewall threshold voltage by both avoiding excess boron segregation into the field oxide, and providing a smoother edge rounding than that obtained by a classical LOCOS process.Heterostructure barrier varactors on copper substrate
http://dl-live.theiet.org/content/journals/10.1049/el_19990255
The authors demonstrate a fabrication process where heterostructure barrier varactor diodes are fabricated on a copper substrate which offers reduced parasitic losses and improved thermal conductivity. This has been achieved without degrading the electrical characteristics.Smart-Cut® process using metallic bonding: Application to transfer of Si, GaAs, InP thin films
http://dl-live.theiet.org/content/journals/10.1049/el_19990663
The ability to obtain thin films using the Smart-Cut® process combined with metallic bonding is demonstrated. New structures have been realised from thin films of Si, GaAs or InP bonded to silicon substrates via metallic layers.Lateral insulated gate bipolar transistor (LIGBT) structure based on partial isolation SOI technology
http://dl-live.theiet.org/content/journals/10.1049/el_19970587
A new LIGBT structure based on partial isolation SOI technology is proposed and demonstrated through numerical simulations. In comparison with conventional SOI LIGBTs, the new structure offers an enhanced RESURF (REduced SURface Field) effect and improved heat dissipation with no compromise in the switching speed and on-state resistance.Si/SiGe <i xmlns="http://pub2web.metastore.ingenta.com/ns/">n</i>-channel modulation-doped field effect transistor on air
http://dl-live.theiet.org/content/journals/10.1049/el_20020706
Si/SiGe <i xmlns="http://pub2web.metastore.ingenta.com/ns/">n</i>-channel modulation-doped field effect transistors (MODFETs) have been fabricated on a 10 µm-thick membrane by removal of the Si substrate and SiGe virtual substrate under the device layers. The membrane devices, surrounded by air, were characterised after thinning and compared to the unthinned characteristics. A large reduction of the off-currents of the MODFETs on air, due to an increase in substrate resistance, has been measured, making them more suitable for low-power applications.Use of polyimide bonding for hybrid integration of a vertical cavity surface emitting laser on a silicon substrate
http://dl-live.theiet.org/content/journals/10.1049/el_19970752
The use of polyimide bonding for hybrid integration of a vertical cavity surface emitting laser on an Si substrate was demonstrated. The threshold current was 3.1 mA and the maximum output power was 2.45 mW for a 15 µm diameter mesa. This technology is suitable for integrating photonic devices with an Si-LSI circuit.Low temperature GaAs/Si direct wafer bonding
http://dl-live.theiet.org/content/journals/10.1049/el_20000507
GaAs-Si low temperature bonding has been achieved using spin-on-glass as the intermediate layer. Interface energies of ~1.7 J/m<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">2</sup> were obtained after thermal annealing at only 200°C. The interface energy is sufficiently high to allow thinning of the GaAs wafer down to 5–10 µm.Johns Hopkins on the chip: microsystems and cognitive machines for sustainable, affordable, personalised medicine and healthcare
http://dl-live.theiet.org/content/journals/10.1049/el.2011.3233
Semiconductor technology is contributing to the advancement of biotechnology, medicine and healthcare delivery in ways that it was never envisioned – from chip micro-arrays, to scientific grade CMOS imagers and ion sensing arrays to implantable prosthesis. This exponential growth of sensory microsystems has led to an exponential growth of data. Cognitive machines, i.e. advanced computer architectures and algorithms, are carefully co-designed to extract knowledge from such health data making rational decisions and recommendations for therapies. Nano, micro and macro robotics driven by sophisticated algorithms interface to the human body at different levels and scales, from nano-scale molecules to micron-scale cells to networks and all the way to the scale of organisms. The present era is one where semiconductor technology and the ‘chip’ is the foundation of sustainable and affordable personalised medicine and healthcare delivery.High cleanliness of portable clean-unit-box to unite clean-unit system platforms (CUSPs) and CUSP units
http://dl-live.theiet.org/content/journals/10.1049/el_20072096
As a platform for nano-science and technology, cleanliness in a compact and local clean environment, i.e. a portable clean-unit-box (CUP), is reported for establishing a large-scale network of an ultra-high clean environment platform towards cross-disciplinary research. Analyses of experimental results indicate that the CUP has cleanliness of ISO class ∼2, which is one order of magnitude better than the conventional wafer transportation cleanbox.Transistor action in GaP/TmP/GaAs heterostructure
http://dl-live.theiet.org/content/journals/10.1049/el_20010771
Transistor action in a gallium phosphide/thulium phosphide/gallium arsenide (GaP/TmP/GaAs) structure with a GaP emitter, TmP base, and GaAs collector is reported. The emitter-base junction was constructed through wafer bonding and the base-collector junction was formed by epitaxial growth of TmP on GaAs in a molecular beam epitaxy system. From the I-V measurements, a common base current gain α ≃ 0.55 measured at <i xmlns="http://pub2web.metastore.ingenta.com/ns/">V<sub>CB</sub></i> = 0 was obtained at room temperature.Transfer of 3 in GaAs film on silicon substrate by proton implantation process
http://dl-live.theiet.org/content/journals/10.1049/el_19980265
For the first time, transfer of a thin monocrystalline GaAs film from its original bulk substrate onto a silicon substrate was achieved by proton implantation and wafer bonding. Successful transfers of 3 in GaAs film are presented.Silicon carbide on insulator formation using the Smart Cut process
http://dl-live.theiet.org/content/journals/10.1049/el_19960717
The Smart Cut process has been applied for the first time to SiC, in order to form silicon carbide on insulator (SiCOI) structures. These structures have been formed on polycristalline SiC and on silicon substrates.Rapid determination of long generation lifetime
http://dl-live.theiet.org/content/journals/10.1049/ip-g-2.1992.0001
The determination of the long generation lifetime by using the Zerbst plot technique or the saturation capacitance technique are timeconsuming. A new rapid technique suitable to determine the long generation lifetime is suggested. This method is based on analysing nonsaturation C-t transient of an MOS capacitor under a linear voltage sweep. A depletion linear voltage sweep at a relatively high rate will drive an MOS capacitor into deep depletion state rapidly. As the capacitance-saturation need not be reached, drawing such a C-t transient curve is time-saving. A simple procedure may be used to extract the generation lifetime from this curve. The experiments show that the measured results are well self-consistent and the method is reasonable and appreciatively time-saving.Chemistry of polymeric resists useful in microlithography
http://dl-live.theiet.org/content/journals/10.1049/ip-i-1.1983.0043
Polymer resists are indispensible to modern-day manufacture of integrated circuits and, to be effective, demand special combinations of many properties, such as sensitivity and resolution, for particular forms of radiation exposure, adhesion to semiconductor, metals and dielectric layers, resistance to plasma processing techniques and the ability to withstand appropriate thermal treatments. The nature of polymer resists in current usage and the various chemical transformations involved in optical and electron-beam lithography are outlined.Effect of irradiation and annealing conditions on power transistor performance
http://dl-live.theiet.org/content/journals/10.1049/ip-g-2.1993.0061
It is shown that to simultaneously achieve requirements of dynamic (storage time) and static (on-resistance, peak drain current) power transistor characteristics, an irradiation/ anneal processing cycle may be used. This includes annealing at a temperature range limited by the thermal stabilities of the A-centres and divacancies (i.e. 300–380°C). The irradiation flux by high energy electrons is chosen to accumulate the preassigned concentration of A-centres in the epilayer where transistors have been formed. This condition drives the choice towards high flux irradiation (fluxes above 10<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">16</sup>cm<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">−2</sup>) for power transistors. In addition, the irradiation/annealing process imposes constraints on impurity concentrations in the heavily doped drain (or collector) region and in the epilayer. The shallow donor impurity concentration must greatly exceed the oxygen concentration in the heavily doped region and the oxygen concentration must greatly exceed the carbon concentration in the epilayer.Experimental and theoretical investigations of parameters controlling line profiles in electron-beam lithography
http://dl-live.theiet.org/content/journals/10.1049/ip-i-1.1981.0001
An experimental and theoretical investigation of the more important parameters which affect the developed profile shape in electron-beam lithography is described. The theoretical approach is based on a Monte Carlo method of simulating electron scattering in the substrate to calculate the energy dissipation in the electron resist layer for a scanned electron beam. The current distribution in the beam is taken into account with a separate convolution procedure. The developed profile shape is obtained with a threshold solubility model which predicts a threshold energy density of 6.58 × 10<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">21</sup> eV/cm<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">3</sup>. A development simulation using the string method is used to predict the profile shape when the development process becomes a significant factor at a resist thickness of about 0.7μm. Finally the proximity effect is investigated by means of adjacent line experiments and compared with the predictions of the threshold solubility model.Preprocessing of data from spreading-resistance measurements
http://dl-live.theiet.org/content/journals/10.1049/ip-i-1.1980.0019
Spreading-resistance measurements often exhibit a lot of noise which can hinder their analysis. A method is presented for automated elimination of strongly deviating values, and smoothing of the resistance curve, leading in a few filter steps to a more accurate determination of the concentration profile. It is shown that the accuracy of the spreading-resistance technique can be increased by combining several profiles of a sample.V-groove isolated b.i.f.e.t. technology for micropower i.c.s
http://dl-live.theiet.org/content/journals/10.1049/ip-i-1.1980.0036
This paper describes a V-groove isolated b.i.f.e.t. technology suitable for micropower integratedcircuit fabrication. The V-groove isolation technique offers considerable advantages in area and performance over standard junction isolated technology. The technology provides an ideal combination of active elements which include low pinchoff j.f.e.t.s and bipolar transistors. The characteristics of the devices as well as typical applications of the technology are described.Silicon-on-insulator technology
http://dl-live.theiet.org/content/journals/10.1049/ip-i-1.1986.0017
The last few years have seen considerable progress in the development of techniques for producing silicon-on-insulator (SOI) substrates suitable for fabrication of high performance devices/circuits. Among the most promising of the new ideas are those based on buried dielectric formation by ion implantation (oxygen or nitrogen), recrystallisation of deposited polycrystalline silicon-on-insulator (using lasers, electron beams, hot wires, strip heaters or incoherent light), and oxidation of porous silicon. A number of other techniques also show potential. The concept of SOI is not new, however. Attempts to grow single crystal semiconductor films on insulating substrates date back almost 40 years with the first successes in the growth of silicon layers in the early 1960s. During that period epitaxial silicon-on-sapphire (SOS) emerged as a viable approach to SOI, since when it has become a well established technology for MOS with a unique role to play in some important areas of application. The new substrate types promise to extend the range of applicability still further. Indeed, some workers predict a revolution, following which, for MOS technology at least, single crystal silicon substrates will play a minor role in comparison to SOI. This paper outlines these different approaches to SOI and reviews their advantages for a number of important application areas, placing particular emphasis on MOS technology. Applications such as VLSI, memory, structured, random and high speed logic, analogue circuit design and defence electronics are considered. Recent developments in the preparation of SOI substrates have led to the successful realisation of a range of novel ‘stacked’ structures exploiting, for example, two (or more) independent layers of devices, common gates or common device channels. Progress in and the potential of this exciting new field of three-dimensional integration is reviewed also.Langmuir-Blodgett electron-beam resists
http://dl-live.theiet.org/content/journals/10.1049/ip-i-1.1983.0044
The Langmuir-Blodgett(LB) technique is a new way of applying resist to a substrate for microstructure fabrication. It provides a layer of much greater homogeneity and uniformity than is possible with conventional techniques, advantages expected to be of special importance in electron-beam lithography. The paper reviews work published in this field, which covers both positive- and negative-contrast materials. Several have characteristics which are competitive with those of existing resin resists, and chemical modifications are suggested for even greater improvement. New experimental results are presented, which show that the time required for application of an LB resist layer need not be incommensurate with that of other lithographic steps.Rutherford scattering analysis: a tool for semiconductor-device technology
http://dl-live.theiet.org/content/journals/10.1049/ij-ssed.1977.0001
In the paper we consider how the Rutherford scattering of high-energy (MeV) light ions can be used as a nondestructive technique for studying thin films on semiconductor surfaces. A number of examples are discussed which illustrate the potential and limitations of the technique for studying semiconductordevice structures.Design and development of a lab-model silicon epitaxial reactor
http://dl-live.theiet.org/content/journals/10.1049/iipi.1975.0010
A semiautomatic, horizontal type silicon epitaxial reactor has been designed, fabricated and utilised. All the design aspects such as cleanliness, compactness and streamlined structure of the reactor for handling upto four 1½″ diameter wafers have been taken into account. The design of reactor is simple and utilises around 90% indigenous components. The present model is designed for premixed doped silicon tetra-chloride but can be modified easily for gas doping also.Device quality epi-layers both on <i xmlns="http://pub2web.metastore.ingenta.com/ns/">n</i><sub xmlns="http://pub2web.metastore.ingenta.com/ns/">+</sub> and <i xmlns="http://pub2web.metastore.ingenta.com/ns/">p</i> substrates for discrete devices as well as integrated circuits have been obtained. The main specifications are:1. Thickness variation from wafer to wafer is 1 to 2 microns and edge variation of wafer is ± 0·5 microns.2. Resistivity variations from wafer to wafer is ± 0·5 ohm-cm and edge variation on a wafer is + 0·25 ohm-cm.3. Stacking fault density is less than 100/sq. cm.