New Publications are available for Analogue processing circuits
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New Publications are available now online for this publication.
Please follow the links to view the publication.40 Gb/s distortion mitigation and DSP-based equalisation
http://dl-live.theiet.org/content/conferences/10.1049/ic_20070121
Different aspects of electronic distortion equalization at 40 Gbit/s are highlighted: from the experimental assessment of analog equalizer circuits to the estimation of the digital processing effort in DSP based equalisation schemes. (4 pages)A study of reconfigurable analogue for DRM and HF systems
http://dl-live.theiet.org/content/conferences/10.1049/cp_20030436
This paper focuses on the use of reconfigurable analogue technology to support multi-standard Digital Radio Mondiale (DRM) and high frequency (HF) communication systems. The choice of receiver architecture is discussed within the context of frequency adaptive systems and the low-IF receiver is introduced as an alternative to the zero-IF digital receiver. This paper also investigates the ability of field programmable analogue arrays (FPAAs) to implement matched filters within a low-IF receiver, thus providing the flexibility to support multistandard operation.Design of High Frequency Integrated Analogue Filters
http://dl-live.theiet.org/content/books/cs/pbcs014e
<p xmlns="http://pub2web.metastore.ingenta.com/ns/">This book brings together the leading researchers, in high frequency analogue filters to highlight recent advances and identify promising directions for future development.</p>A comparative study of reconfigurable digital and analogue technologies for future mobile communication systems
http://dl-live.theiet.org/content/conferences/10.1049/cp_20010061
The requirements of 3G and 4G systems dictate that system architectures adapt to various user conditions, i.e. be reconfigurable. The concept of a fully reconfigurable system is fast becoming reality, due to new and advancing enabling technologies. This paper presents two such technologies, the field programmable gate array (FPGA) and field programmable analogue devices (FPAD). These devices provide the reconfiguration functionality for both digital and analogue system architectures.A 200 MHz CMOS analogue-ROM based direct digital frequency synthesiser
http://dl-live.theiet.org/content/conferences/10.1049/ic_20000480
A novel, low power frequency synthesiser system with 60 MHz output bandwidth is reported which is suitable for integration in a single chip RF transceiver. The system is based upon a conventional DDFS architecture. However, the problems which usually arise from the non-ideal behaviour in the DAC and the high power consumption of a ROM are avoided by using a non-volatile analogue memory array. Simulation results are presented which show that the system is suitable for use in an RF transceiver. (6 pages)A current-mode analog multiplier using a negative resistance transconductance technique
http://dl-live.theiet.org/content/conferences/10.1049/ic_20000490
A current-mode multiplier based on a negative resistance transconductance circuit is proposed as the input stage for the Gilbert transconductance multiplier circuit. Compared with the input stage of the standard Gilbert multiplier which is based on an emitter degenerated long-tail pair, the negative resistance transconductance cell provides better linearity, accuracy and noise performance. Also the gain of the overall circuit is significantly higher. (6 pages)Logarithmic converter based on a transconductance feedback amplifier
http://dl-live.theiet.org/content/conferences/10.1049/ic_20000481
This paper demonstrates how the problem of significantly reduced logarithmic converter bandwidth at lower signal levels may be almost entirely eliminated by direct substitution of a transconductance feedback amplifier (TFA) in place of the standard voltage operational amplifier (VOA). Taking advantage of the constant loop-gain mode of operation of a TFA permits virtually constant bandwidth to be obtained throughout the log converter's full input signal range. (4 pages)A new adaptive architecture: analogue synthesiser of orthogonal functions
http://dl-live.theiet.org/content/conferences/10.1049/cp_19991195
A new adaptive nonlinear (neural-like) architecture, an analogue synthesiser of orthogonal functions which is able to produce a plurality of mutually orthogonal signals as functions of time such as Legendre, Chebyshev and Hermite polynomials, cosine basis of functions, smoothed cosine basis, etc., is proposed. A proof-of-concept breadboard version of the analogue synthesiser is described. The device is characterised by a very fast (approximately 100 iterations) and stable process of signal synthesis. The proposed new device could find applications e.g. in analogue systems of function approximation, in particular as a main unit in an analogue implementation of so-called Chebyshev polynomial-based (CPB) neural networks, as a unit in a fast adaptive alternative to Volterra polynomial neural networks, and also as a preprocessing element (performing some transforms, filtration, etc.) in analogue neural network-based systems of information processing.Towards a fully implantable analogue cochlear prosthesis
http://dl-live.theiet.org/content/conferences/10.1049/ic_19980852
This paper addresses the feasibility of a completely new design of cochlear prostheses replacing all digital signal processing by an analogue signal processor. The new design is based upon CMOS-VLSI transistors operating in weak inversion and in micro-power mode. Lowpass and bandpass filters are designed using the recently proposed log-domain technique. The proposed analogue system is smaller and consumes less power then most conventional devices. (11 pages)The K-model: RF IC modelling for communication systems simulation
http://dl-live.theiet.org/content/conferences/10.1049/ic_19980853
A new technique for modelling the entire analogue front-end of an RF IC for fast simulation and analysis in a DSP design environment is described. The designer's objective is to see if an existing analogue front-end circuit design will work in the target end-to-end system before the RF IC is fabricated. Accurate full system simulation might save the need for chip redesign, mask generation and refabrication. A wireless receiver's analogue front-end circuitry introduces varying levels of distortion dependent on carrier bias. To simulate the RF front-end in a system simulation, time-domain based behavioural models, K-models, are used to represent the receiver's nonlinear effects. With SpectreRF's periodic AC and periodic noise analyses the receiver's nonlinear frequency translating and noise effects are accurately characterized. A scripting language called OCEAN<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">TM</sup> is used to write an extraction program to run SpectreRFM simulations and save the necessary base-band to base-band frequency response and power spectral density data files. K-models reside in the signal processing work system (SPW<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">TM</sup>) as block diagram symbols. The K-model uses the SpectreRFM data from the extraction simulation to define its nonlinear performance. Full end to end system simulations are then analyzed within SPW<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">TM</sup>. The K-model behavioural simulation approach is found to be extremely fast when compared with full circuit transistor level simulation techniques. (8 pages)Low noise, high linearity Gilbert cell transconductor
http://dl-live.theiet.org/content/conferences/10.1049/ic_19980850
This paper describes techniques to reduce the effects of parasitic emitter resistance in the Gilbert current gain-cell. The technique is further developed to be employed in a Gilbert cell transconductor (GCT), which offers improved characteristics in terms of linearity and noise performance over the conventional GCT. The deliberate addition of resistors to the gain-cell offers a better noise performance than that of the conventional GCT, while an improvement in linearity is achieved by using a transconductance summation technique to give an overall flatter response. (15 pages)A DFT technique to increase the resolution of AC RMS power supply current monitoring of complex analogue circuits
http://dl-live.theiet.org/content/conferences/10.1049/ic_19971200
RMS AC supply current monitoring with the addition of the novel DFT technique presented in this paper shows an increase in fault coverage for an embedded opamp from only 2.5% to over 70%. During a test, the effective width-length ratio of the transistors that draw the most AC current is reduced, causing the supply current drawn by other parts of the circuit that might be faulty to contribute relatively more to the overall supply current, allowing detection of faults. The results of Monte Carlo fault simulations demonstrate the principle. The most significant advantages of this DFT technique are increased fault coverage; small (1%) area overhead; and low impact on the performance of the circuit. (5 pages)Field programmable analogue arrays: a DFT view
http://dl-live.theiet.org/content/conferences/10.1049/ic_19971193
The design for testability (DFT) of analogue and mixed signal electronic systems has much in common with the problem of Field Programmable Analogue Array (FPAA) design. The FPAA described here is offered as a model for analogue system DFT It gives direct access to internal nodes of the user circuit, it facilitates subdivision for modular test and it can reconfigure the circuit to comply with standard test usage. Special switching techniques are employed to prevent the DFT enhancement detracting from the performance of the circuit in service. A prototype of this FPAA architecture has been fabricated on standard CMOS and a summary of performance is presented. (4 pages)ANTICS analogue fault simulation software
http://dl-live.theiet.org/content/conferences/10.1049/ic_19971204
The increasing size and complexity of analogue and mixed signal ICs combined with market pressures of increased quality levels and reduced cost has led to an interest in structural test methods for analogue and mixed-signal ICs. The aim of such tests is to verify the integrity of the circuit by detecting manufacturing defects directly, rather than through the resultant functional specification error. In order to quantify the effectiveness of a structural test through simulation, manufacturing defects are represented using simulation fault models. By comparing the simulation output from a fault-free circuit and that of a circuit with a simulation fault model injected into it, a measure of the detectability of a fault for a given structural test can be obtained. This is the principle of the ANTICS analogue fault simulation software which is described in this paper. (5 pages)Improvements to circuit diagnosis through hierarchical modelling
http://dl-live.theiet.org/content/conferences/10.1049/ic_19971202
The testing of large scale analogue integrated circuits has become increasingly significant with the advent of mixed signal ASICs, of which circuit size and complexity are ever increasing. The domain for analogue circuit testing is at present lagging behind its digital counterpart on which a lot of development has been done, leading to a very mature technology and many comprehensive software tools. Over the years, many different approaches have been proposed to tackle the complex issue of analogue testing. Amongst them is a powerful approach introduced by Wey (1987). This employs a Self Test (ST) Algorithm formulated on the Component Connection Model (CCM). We have improved on the approach of Wey in proposing an Optimal Tree Generation (OTG) Algorithm in conjunction with a novel Test Point Selection Procedure to select a set of test points to diagnose a given maximum number of possible faults. In this paper the authors propose two addition enhancements in the diagnosis procedure to compensate for the insufficiencies of their earlier works. These enhancements are namely, the partition generation algorithm and the backtracking of test results. The modifications needed for the adoption of a hierarchical approach into the diagnosis procedure are also discussed, These are the imposing of a hierarchical partition rule for tester/testee partition in every test cycle and the re-interpretation of the decision algorithms at the circuit graph level to consider the effect of hierarchical graph edges. (6 pages)Integrated intelligent electrodes for electrical capacitance tomography
http://dl-live.theiet.org/content/conferences/10.1049/ic_19960843
Preliminary investigations are described that consider the architecture for an electrical capacitance tomography system in which the processing circuitry for each `channel' is mounted directly onto each electrode. The work is motivated by the desire to improve signal-to-noise by increasing the operating frequency. This, in turn, requires reduction of stray capacitance. Almost all of the electronic circuitry is included on a custom silicon integrated circuit that is implemented using a high voltage BiCMOS technology. The chip includes the front-end charge-discharge circuit with differential amplification, programmable gain and offset compensation, and analogue-to-digital conversion. Data communication with the host is via a serial shift register and each electrode requires less than 10 electrical connections. (4 pages)Novel Palmo analogue signal processing IC design techniques
http://dl-live.theiet.org/content/conferences/10.1049/ic_19961252
Introduces and analyses a novel technique for implementing programmable analogue hardware. Novel programmable Palmo circuits have been introduced which have low switching noise, low THD, and may be configured to perform many signal processing functions. An initial test chip has demonstrated the viability of the approach and aided in understanding the practical application of the technique. This has led to new ideas for the implementation of the Palmo building blocks to reduce THD and improve overall programmability and performance. Such circuits are ideal for field programmable analogue array (FPAA) cells. The new Palmo circuit blocks have a dedicated 6-bit current DAC and 3-bit programmable capacitor array giving 9 bits of programmability per cell. Cell interconnect to local neighbours or to pads further enhances programmability and high frequency performance. Dedicated static RAM is used to store the cell parameters and interconnect-which may also be dynamically reconfigured. A new improved comparator is under development to reduce harmonic distortion at high frequencies. These circuits are currently being designed and a new chip is to be fabricated in the near future. (6 pages)Switched-capacitor filters for FPGA implementation: tools and designs
http://dl-live.theiet.org/content/conferences/10.1049/ic_19961266
Traditionally, the accuracy requirements demanded by high quality integrated filters could only be satisfied by full-custom fabrication. Recent developments in analogue FPGA facilities present opportunities to a wider community of designers for commercial realisation of integrated circuit filters suited to a reasonable range of applications. Software to support filter design within the overall facility enables easy access to standard filtering functions. It is hoped to provide advanced features for more sophisticated design as the facility develops. (7 pages)Whispers Generic Control Processor (GCP) - a unique ASIC solution to analogue filtering using digital techniques
http://dl-live.theiet.org/content/conferences/10.1049/ic_19961262
Whispers (GCP) is an integrated ADC, DSP, and DAC providing a complete analogue processing solution for audio frequency applications. It provides all the advantages of digital filtering techniques and the reprogrammability associated with it, but without the overhead of a traditional DSP solution and in many cases a system latency and power consumption not otherwise achievable. Whispers achieves an overall noise performance of 80dB, and features low latency processing making it particularly suitable for repetitive, time critical applications. The custom DSP core performs a single-cycle multiply-accumulate, and has been extended to efficiently address cascaded second order IIR filter applications. The core also features multiple instruction execution, and a single level instruction pipeline enabling zero-overhead subroutine branching. (7 pages)Evolutionary design of analogue electronic circuits; current status
http://dl-live.theiet.org/content/conferences/10.1049/ic_19961254
Analogue circuit design optimisation has for a long time been treated classically through a number of conventional optimisation techniques such as gradient methods or Hill-Climbing techniques. The component values produced by these conventional methods are typically assumed to be ideal with unrestricted values in a circuit configuration that is pre-defined. Therefore it would be very desirable to perform the search for an optimum design in a solution space that more closely reflects partial applications. Here, components may be restricted to have values that are selected from a menu of pre-defined preferred values, and have associated imperfections such as individual parasitics. It is further desirable that the circuit structure not be pre-defined since in general it would not be known to be optimal, but be included with the optimisation process. In this form, the optimisation problem is very complex with many local minima. These difficulties have suggested the use of evolutionary optimisation methods. The aim of this paper is to review progress to date and to describe some work in hand, on the evolutionary design of analogue electronic circuits. The use of genetic algorithms is more widely reported and dealt within this paper. (8 pages)A field programmable, current mode, analog VLSI
http://dl-live.theiet.org/content/conferences/10.1049/ic_19961253
This work describes the architecture of a reconfigurable VLSI device which can be programmed to perform a wide range of analog signal processing functions. The device is to be constructed using a standard, single-well, CMOS process with the facility for construction of linear, parallel plate capacitors. The device operates in continuous time and therefore requires no sampling clock. It implements both linear and non-linear transfer functions over a useful bandwidth of approximately 100 kHz. (6 pages)ASICS for integrated sensors
http://dl-live.theiet.org/content/conferences/10.1049/ic_19951508
This paper will present three case studies of sensor applications where the use of Application Specific Integrated Circuits (ASICs) has enhanced the performance of the sensor realisations. The paper will discuss two sensor systems, developed by the authors, which utilise a current-mode interface. These are current-mode analogue signal processing ASIC as part of both an electronic nose and a Wedge and Strip Anode (WSA) charged particle detector. The third case study will concentrate on a novel ultrasonic transducer receive system which has been developed. This too utilises ASIC technology and an account of progress to date will be presented. (8 pages)Behavioural macromodelling for analogue fault simulation
http://dl-live.theiet.org/content/conferences/10.1049/ic_19951207
This paper describes the modelling of bridging defects in analogue circuits as changes to the external, observable characteristics of the circuits. By considering the behaviour of operational amplifier circuits configured to perform particular circuit functions, the varieties of faulty operation are reduced in number and the defective behaviours can be grouped together. This can reduce the overall number of faults to be simulated by 50%. As we are modelling the functional behaviour of circuit blocks, we need to generate macromodels of those blocks. Of particular interest to us has been the modelling of the supply current. (6 pages)AC analysis of time discrete systems
http://dl-live.theiet.org/content/conferences/10.1049/ic_19951201
Analogue circuit simulators to-date do not allow AC analysis of transistor-level mixed-signal circuits. Simulators such as ELDO or SwitCap provide specially developed tools for AC analysis of switched capacitor circuits, but the element models are crude and do not allow consideration of “all” parasitic effects such as parasitic capacitances or charge feedthrough effects in transistors. Also they do not allow final netlist simulation of a circuit directly against its frequency domain specifications. Furthermore, with such tools it is not possible to obtain information on, for example, the influence of process variations, and the affect of temperature on frequency domain parameters such as the centre-frequency of a band-pass filter. To give a possible solution to this shortcoming of existing simulator technology, a route has been developed for ELDO to comfortably extract the important frequency domain information from time domain simulations. The amount of output information is kept to an absolute minimum and the results can be viewed directly with a graphical tool which is part of the ELDO suite of simulation utilities. Current work is looking into a servo-sensor system, a switched-capacitor filter, and a ΣΔ-modulator, to demonstrate the feasibility and usefulness of this approach. This paper describes this approach, and will highlight the background to the results obtained in the accompanying presentation. It is assumed that this method for frequency domain analysis can easily be integrated into existing analogue circuit simulators. (7 pages)Advanced modeling techniques for subthreshold and full chip simulation
http://dl-live.theiet.org/content/conferences/10.1049/ic_19951208
For over 20 years, Berkeley SPICE and SPICE-like programs have been the standards for use in electrical circuit simulation. Over time, however, circuit simulation demands have changed and as a result, simulation techniques must change, as well. SPICE was originally designed to simulate circuits with device counts of order 100, while today designers would like to simulate circuits with hundreds of thousands of devices. In addition, the character of analog circuits is changing, as many designers want to operate transistors in subthreshold, in an effort to minimize power dissipation. In order to meet the accuracy demands of subthreshold designers, new transistor models, such as the Maher-Mead model available in Tanner Research's T-Spice simulator, have been developed. These transistor models match the physical device behavior much better than the standard SPICE transistor models. But accuracy comes at the expense of speed. In order to allow fast simulation with these state-of-the-art models, table techniques can be used to store computed model values so that the total number of model evaluations is kept low. These table techniques are useful not only to the analog subthreshold designer, but also to the digital designer, as using these techniques allows the simulation of very large circuits, even full chips. (3 pages)DYMPLES - an analogue current mode pulsed synapse
http://dl-live.theiet.org/content/conferences/10.1049/cp_19950603
Several artificial neural network (ANN) implementations require two-quadrant multiplications for neural state computations. Almost all previous analogue hardware implementations of two-quadrant multipliers for ANNs have used circuits operating in voltage mode. In the paper a chip consisting of synapses using current mode principles is presented. By basing the multiplier circuits on dynamic current mirrors, the aspirations were to produce synapse arrays that were easy to set up, were robust and cascadable and that also possessed better process tolerance than previous voltage mode devices. The hardware results presented from the Dynamic Mirror Pulsed Experimental Synapse (DYMPLES) chip are extremely encouraging, fulfilling all initial aspirations and showing that the synapse design does indeed possess the potential for process tolerance.High-quality factor asymmetric-slope band-pass filters: a fractional-order capacitor approach
http://dl-live.theiet.org/content/journals/10.1049/iet-cds.2011.0239
This study presents new techniques for implementing continuous-time second-order band-pass filters with high-quality factors and asymmetric slopes. The techniques are centred around the realisation of two non-conventional transfer functions which include the non-integer-order Laplacian operator <i xmlns="http://pub2web.metastore.ingenta.com/ns/">s</i><sup xmlns="http://pub2web.metastore.ingenta.com/ns/">α</sup>; 0<α<1. Four main possible circuit realisations; one based on a frequency-dependent negative resistor (FDNR), another based on an inductor and two based on multiple amplifier biquads (MABs) are given and verified using Spice and experimentally for both transfer functions. In addition, a field programmable analogue array (FPAA) realisation is tested and verified. Last but not least, a possible realisation using current conveyors is also given, tested and verified.Continuous-time envelope-constrained filter design via DSP approach
http://dl-live.theiet.org/content/journals/10.1049/ip-vis_20010672
In envelope-constrained (EC) filter design, the effect of input noise is minimised subject to the constraint that the filter's response to a specified signal fits into a prescribed envelope. The continuous-time version of this problem has been addressed using orthonormal analogue filters. The paper addresses the EC filter-design problem using a filter comprised of an A/D converter, a digital processor, a D/A converter and an analogue interpolation filter. Numerical results are presented for a number of design examples.Direction-of-arrival estimation method based on six-port technology
http://dl-live.theiet.org/content/journals/10.1049/ip-map_20050239
A new direction-of-arrival estimation method based on six-port technology is presented. In order to obtain the beam direction, the proposed circuit uses a two-channel multi-band receiver and analogue signal processing of the six-port circuit output signals. A practical approach for estimating the beam direction has also been proposed. This approach, based on the detection of the minimum magnitude of the in-quadrature output signal, avoids the necessity of computing the angle-of-arrival value. A dual-band prototype circuit was designed and fabricated. Simulation results in the S and C frequency bands are presented and discussed. In order to validate this method, measurements were carried out in the C-band. These results show a maximal angle-of-arrival estimation error of about 3%. Therefore, low-cost direction-of-arrival measurements can be performed using this new method.Square-rooting and vector summation circuits using current conveyors
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19951951
New analogue squaring, square-rooting and vector summation circuits using current conveyors (CCIIs) are presented. They consist of MOS transistors biased in the triode region, a buffered unity-gain inverting amplifier, resistors and CCIIs. A general n-input vector summation circuit is also proposed. The proposed squaring, square-rooting circuits and a two-input vector summation circuit have been implemented using commercial CCIIs and transistor arrays. Its -3 dB bandwidth is measured to be about 400 kHz. The proposed circuits are expected to be useful in analogue signal-processing applications.Clock feedthrough analysis and cancellation in current sample/hold circuits
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19941532
The clock feedthrough current caused by charge injection in a current sample/hold circuit is investigated. After an overview of the existing cancellation techniques, a novel technique for cancelling both signal-dependent and signal-independent clock feedthrough current is introduced. The narrow channel width effect on the output current of a nonunity current mirror and the clock feedthrough voltage at the gate of the holding transistor are also analysed and simulated using HSPICE. Results show that the proposed circuit not only cancels both signal-dependent and signal-independent clock feedthrough current, but also does not suffer from the narrow channel width effect. The proposed technique is superior to other techniques in terms of clock feedthrough current error, speed and silicon area.Low-voltage CMOS four-quadrant multiplier based on square-difference identity
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19960479
A low-voltage CMOS four-quadrant multiplier based on the square-difference identity ([<i xmlns="http://pub2web.metastore.ingenta.com/ns/">a</i> + <i xmlns="http://pub2web.metastore.ingenta.com/ns/">b</i>]<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">2</sup> – <i xmlns="http://pub2web.metastore.ingenta.com/ns/">a</i><sup xmlns="http://pub2web.metastore.ingenta.com/ns/">2</sup> – <i xmlns="http://pub2web.metastore.ingenta.com/ns/">b</i><sup xmlns="http://pub2web.metastore.ingenta.com/ns/">2</sup>) is presented. This circuit has been implemented in a 0.8 µm single-poly double-metal <i xmlns="http://pub2web.metastore.ingenta.com/ns/">n</i>-well CMOS process. Experimental results show that for a power supply of ±1.5 V, the linear input range of this multiplier is within ±0.5 V with the linearity error less than 1%. The total harmonic distortion is less than 1% with input range up to ±0.5 V. The –3 dB bandwidth of this multiplier is measured to be about 1 MHz. Moreover, it can operate satisfactorily regardless of the transistor body connection. This circuit is expected to be useful in low-voltage analogue signal-processing applications.Op-amp based CMOS field-programmable analogue array
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_20000030
The field-programmable analogue array (FPAA) is crucial to improving turnaround time for analogue circuit designs. The critical parameters when specifying the design are bandwidth and accuracy. FPAAs reported to date compromise one parameter when optimising the other. A new continuous-time FPAA architecture is presented which simultaneously achieves bandwidth and repeatability comparable to the accuracy tolerance of switched-capacitor FPAAs and the bandwidth of continuous-time FPAAs. It uses continuous-time operation for high bandwidth and introduces buffered CMOS pass-switches and ratioed function blocks to overcome accuracy limitations. A prototype circuit is presented and applied to op-amp based circuits. The results show that the new FPAA offers the best combination of bandwidth and accuracy published to date.Analogue divider using integral compare mode and its application
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19990226
An analogue divider of integral compare mode which basically consists of two integral operators, a comparator and three electronic switches is described. The circuit has been applied to test the voltage ratio of varistors. Experiments show that it can meet the demand for precision in practical applications by circuit design and the deliberate choice of the devices and elements concerned.CMOS analogue neurone circuit with programmable activation functions utilising MOS transistors with optimised process/device parameters
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19971401
In on-chip learning feedforward and feedback neural networks, different nonlinear activation functions are required. To date, these different functions are realised by physically changing the activation circuits. A novel CMOS analogue circuit suitable for modelling neurons with programmable activation functions is introduced. The proposed circuit is realised by optimising the second-order components of MOS transistors. Programmability of the activation function is achieved using an external controlling signal. Intensive simulations based on SPICE3 indicate that the proposed circuit can realise different activation functions including step, linear threshold, and sigmoid functions.Four-quadrant analogue CMOS multiplier cell for VLSI signal and information processing
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19981846
A CMOS four-quadrant analogue multiplier cell for VLSI signal and information processing based on a transconductor and associated circuitry to cancel nonidealities is presented. It is designed to operate in the triode region. This multiplier is modular, has a large dynamic input range, high linearity, low power dissipation and can provide either a differential output current or voltage. The design was fabricated using a 1.2 µm CMOS process. Simulation and experimental results are presented and discussed.Time-domain fault diagnosis of analogue circuits in the presence of noise
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19981744
An approach to multiple fault diagnosis in dynamic linear and nonlinear circuits based on testing of actual and simulation of nominal circuit is presented. Time domain integral sensitivity is used for constructing test equations. An adaptive algorithm for selecting time intervals for integral sensitivity is included. The least squares approach (LSA) to solve overdetermined diagnosis equations with noisy data is used in conjunction with the regularisation method of Tikhonov. Three illustrative examples show applications of the method.Comment: Square-rooting and vector summation circuits using current conveyors
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19981590
Tracking switched-capacitor CMOS current reference
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19981736
An integrated CMOS current reference is presented, based on the switched-capacitor (SC) circuit technique. The output current is obtained by applying a given reference voltage, using a feedback loop, to an SC structure which emulates a resistor. The reduced spread in SC equivalent resistor values, combined with the high accuracy in integrated voltage references, ensures low dispersion in the generated current. The obtained current tracks the capacitance per unit area of the structure used to integrate the capacitors. The circuit is therefore useful for biasing operational amplifiers and other active circuitry in high-frequency SC or switched-current analogue processors.A low-power low-noise CMOS analogue multiplier
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_20045165
A low-power and low-noise analogue multiplier operating with 1.5 V supply voltage is presented. The core structure consists of only six transistors and brings in the benefits in terms of linearity, power consumption and noise performance. Some design considerations are also provided. The extensive experiments with SPICE simulation show that this new structure is particularly attractive for low-power and low-noise applications in comparison with other previously reported structures.Design and analysis of a ±1 V CMOS four-quadrant analogue multiplier
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19981823
The design and analysis of a ±1 V CMOS four-quadrant analogue multiplier and a frequency doubler for low-voltage low-power applications are presented. The design is based on the current-mode approach and the square-law characteristics of an MOS transistor in saturation. The multiplier utilises I–V converters, a current mirror and four matched transistors to achieve a transresistance gain of 73 dBΩ, a –3 dB bandwidth of 4.3 MHz, a total harmonic distortion below 1% and a maximum power dissipation of 130 µW. Design guidelines have been set to link the circuit performance, in terms of the gain, the input operating range, the fabrication area, and the device aspect ratios, to key device and technology parameters. The scope for further performance improvement using BiCMOS is also highlighted. The experimental results obtained from the chip were found to be in close agreement with the simulated results.Compact analogue neural network: a new paradigm for neural based combinatorial optimisation
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19990314
The authors present a new approach to neural based optimisation, to be termed as the compact analogue neural network (CANN), which requires substantially fewer neurons and interconnection weights as compared to the Hopfield net. They demonstrate that the graph colouring problem can be solved by using the CANN, with only <i xmlns="http://pub2web.metastore.ingenta.com/ns/">O</i>(<i xmlns="http://pub2web.metastore.ingenta.com/ns/">N</i>) neurons and <i xmlns="http://pub2web.metastore.ingenta.com/ns/">O</i>(<i xmlns="http://pub2web.metastore.ingenta.com/ns/">N</i><sup xmlns="http://pub2web.metastore.ingenta.com/ns/">2</sup>) interconnections, where <i xmlns="http://pub2web.metastore.ingenta.com/ns/">N</i> is the number of nodes. In contrast, a Hopfield net would require <i xmlns="http://pub2web.metastore.ingenta.com/ns/">N</i><sup xmlns="http://pub2web.metastore.ingenta.com/ns/">2</sup> neurons and <i xmlns="http://pub2web.metastore.ingenta.com/ns/">O</i>(<i xmlns="http://pub2web.metastore.ingenta.com/ns/">N</i><sup xmlns="http://pub2web.metastore.ingenta.com/ns/">4</sup>) interconnection weights. A novel scheme for realising the CANN in hardware form is discussed, in which each neuron consists of a modified phase locked loop (PLL), whose output frequency represents the colour of the relevant node in a graph. Interactions between coupled neurons cause the PLLs to equilibrate to frequencies corresponding to a valid colouring. Computer simulations and experimental results using hardware bear out the efficacy of the approach.Field programmable analogue array implementation of fractional step filters
http://dl-live.theiet.org/content/journals/10.1049/iet-cds.2010.0141
In this study, the authors propose the use of field programmable analogue array hardware to implement an approximated fractional step transfer function of order (<i xmlns="http://pub2web.metastore.ingenta.com/ns/">n</i>+α) where <i xmlns="http://pub2web.metastore.ingenta.com/ns/">n</i> is an integer and 0 < α < 1. The authors show how these filters can be designed using an integer order transfer function approximation of the fractional order Laplacian operator <i xmlns="http://pub2web.metastore.ingenta.com/ns/">s</i><sup xmlns="http://pub2web.metastore.ingenta.com/ns/">α</sup>. First and fourth-order low- and high-pass filters with fractional steps from 0.1 to 0.9, that is of order 1.1–1.9 and 4.1–4.9, respectively, are given as examples. MATLAB simulations and experimental results of the filters verify the implementation and operation of the fractional step filters.Assessing and comparing fault coverage when testing analogue circuits
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19970870
A new technique for calculating fault coverage when testing analogue circuits is presented. The fault models employed for individual circuit components relate to the importance of those components to overall circuit functionality and therefore permit benchmark assessments and comparisons of fault coverage for different devices, test techniques and test programs. The application of this principle to a simple analogue circuit is demonstrated and the fault coverage obtained, as a function of the detection threshold, employed to differentiate between faulty and fault-free circuit responses, is presented.Low-voltage single power supply four-quadrant multiplier using floating-gate MOSFETs
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19981602
A low-voltage four-quadrant multiplier using floating-gate MOSFETs is presented. This circuit has been implemented in a 0.8 µm double-poly double-metal CMOS process. Experimental results show that for a single power supply of 2.5 V, the total harmonic distortion is less than 1.4% with input range up to 1 V<sub xmlns="http://pub2web.metastore.ingenta.com/ns/">P-P</sub>. The modulation application of this multiplier can be operated over 20 MHz. Moreover, it can operate satisfactorily regardless of the transistor body connection. This circuit is expected to be useful in low-voltage analogue signal processing applications.Novel analogue CMOS defuzzification circuit
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19951927
An analogue CMOS circuit technique for the implementation of defuzzification is proposed. The defuzzification method is based upon the normalisation locked loop (NLL) method, but with two key improvements: the compact representation of triangular membership functions, and a mechanism to ensure that the relative rule weight proportions are preserved during normalisation. Circuit complexity is considerably reduced by combining these two operations in a single circuit stage. The proposed weight circuit, which evaluates normalised rule weights, has been realised using current squaring circuits proposed by Bult and Wallinga (1987). The weight circuit has been fabricated in a 2.0 µm CMOS process. Results obtained from the fabricated circuit operating as part of a NLL are presented.Current-mode defuzzifier circuit to realise the centroid strategy
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19971378
A current-mode circuit based on the square-rooter/multiplier and squarer/divider circuits to realise the centre-of-gravity defuzzification strategy is described. The current-mode approach allows it to operate at 3.3 V without degrading its dynamic range. The proposed circuit was fabricated in 0.8 µm single-polysilicon–double-metal technology, and the experimental results showed that it can operate at high speed with low power dissipation.Analogue realisation of integrated FIR filters
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19960611
The paper presents a unified approach to the design of analogue finite impulse response (FIR) filters. As an analogue realisation the multiphase switched-capacitor technique was chosen owing to its high precision and high packing density in CMOS technology. The proposed design method allows different structures of the filters containing different number of amplifiers to be controlled by different clock signals, providing the best solution taking into account the maximum frequency range and the cost of the chip. Four prototypes of the filters were designed as one integrated circuit using 2 µm double-poly CMOS technology. Measurements made on the test chip confirm the computer simulations. Implementation of interpolation units for analogue FIR filters derived from transversal direct diagram of digital FIR filters is discussed. The linear interpolator provides an improvement to the frequency characteristic of the prototype analogue FIR filter. Computer simulation of the resulting filter has been performed.Programmable gain amplifier with colour balancing for CCD image sensors
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_20040342
The authors present a new programmable gain amplifier (PGA) with colour balancing for single-chip CCD colour image sensors. The PGA with synchronised gain switching allows higher SNR to be achieved in the amplified image while maintaining sufficient gain resolution and low power dissipation. A floating-point expression is used in the designed five-stage pipelined PGA for compact and low-power implementation. Low-noise gain switching with a cross-coupled ring counter sufficiently suppresses the pattern noise due to the high-speed gain switching. The power consumption is 119 mW at 3.3 V supply voltage and 20 MHz pixel rate.Experimental 1-V flexible-IF CMOS analogue-baseband chain for IEEE 802.11a/b/g WLAN receivers
http://dl-live.theiet.org/content/journals/10.1049/iet-cds_20070094
A low-voltage low-power analogue-baseband chain designed for IEEE 802.11a/b/g wireless local-area network (WLAN) receivers is described. It features architecturally a ‘two-step channel selection’ to complement the radio front-end, and a flexible intermediate frequency (IF) reception capability to alleviate the cancellation of frequency and DC-offset. In circuit implementation, a double-quadrature downconverter based on a ‘series-switching’ mixer-quad realises a wideband-accurate I/Q demodulation. A ‘switched-current-resistor’ programmable-gain amplifier (PGA) minimises the bandwidth variation and transient in gain tuning by stabilising, concurrently, the PGA's feedback factor and quiescent-operating point. An ‘inside-OpAmp’ DC-offset canceller creates area-efficiently a very low cut-off frequency high-pass pole at DC while providing a fast settling of DC-offset transients. Fabricated in a 0.35 µm complementary metal-oxide semiconductor (CMOS) process without resorting to any specialised device, the prototype consumes 14 mW per channel at 1 V. The transient time in a 52-dB gain step is <1 µs and the stopband rejection ratio at 20/40 MHz is 32/90 dB. The error vector magnitudes are −27 and −17 dB for 802.11a/g and b modes, respectively.