New Publications are available for Logic circuits
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New Publications are available now online for this publication.
Please follow the links to view the publication.Hardware in the loop based synchronous generator emulation test rig for more electric aircraft power systems
http://dl-live.theiet.org/content/conferences/10.1049/cp.2012.0248
As more electric aircraft power systems grow in complexity and power rating, testing a piece of equipment under realistic operating conditions requires a significant effort in terms of costs and complexity of the experimental test rig. The Power Hardware in-the-Loop (HIL) concept can provide significant advantages in terms of decreased costs and complexity for testing as the performances of a device under test are evaluated in an environment that emulates in real time the behaviour of the remaining components of a complete system. This paper describes the application of the Power HIL concept to the emulation of a wound field synchronous generator of the type used in aircraft power systems. An FPGA based solution is used for real time emulation of the dynamics of the synchronous generator, whereas a bespoke three phase MOSFET based inverter with appropriate output filters, is used as a variable voltage source. (6 pages)A simple capacitor voltage balancing scheme for the cascaded five-level inverter fed AC machine drive
http://dl-live.theiet.org/content/conferences/10.1049/cp.2012.0234
This paper proposes a simple scheme for balancing the series capacitor voltages at the three-phase cascaded five-level inverter fed an induction motor by using the logic circuits. Using switching patterns based on the multi-carrier technique, two series-capacitor voltages can be only balanced during one cycle. However, they have a ripple voltage, which may cause the induction motor drive to be unstable. The proposed scheme for balancing capacitor voltages can be implemented by simple logic circuits. It can be verified that the series capacitor voltages are maintained constant at wide frequency range through experimental results with 32-bit DSP and Cyclone-III FPGA. (5 pages)Discrete hardware controllers design of a single phase PFC boost converter with FPGA
http://dl-live.theiet.org/content/conferences/10.1049/cp.2012.0188
A discrete control design of a single phase PFC boost converter with FPGA is presented. The average current mode control (with current reference) and Self Control (without current reference) are analyzed when implemented with discrete hardware controller. Simulation and experimental results are shown to verify the performance of both controllers. (5 pages)Digital synthetic ripple modulator for point-of-load converters
http://dl-live.theiet.org/content/conferences/10.1049/cp.2012.0220
Hysteretic modulators exhibit superior dynamic performance and without sacrificing the transient response they help to reduce the number of output capacitors. Due to tight regulation requirements modern point-of-load converters have very small output ripple. This small output ripple fails to generate a suitable piece-wise linear modulation waveform for the hysteretic comparator. This paper presents a fully digital Synthetic Ripple Modulator (SRM) comprising of a hysteretic comparator, a ripple synthesizer, and a voltage error amplifier for tight output voltage regulation. The ripple synthesizer realizes a high-quality low-cost current sensors by creating a piece-wise linear synthetic ripple using sensed converter voltages. This artificial ripple is then added to the output voltage and fed as a carrier to the hysteretic comparator. This improves the large signal dynamics of the converter, especially in low voltage application. Analysis and experimental results on a 2 V/10 A, 20 W single phase prototype are presented to verify the operation of the proposed digital SRM. (6 pages)Implementation and testing of multipliers using reversible logic
http://dl-live.theiet.org/content/conferences/10.1049/ic.2011.0073
Reversible logic gates are very much in demand for the future computing technologies as they are known to produce zero power dissipation under ideal conditions. Reversible logic circuits are of interests to power minimization having applications in low power CMOS design, optical information processing DNA computing, bio informatics, quantum computing and nanotechnology. Both reversible logic synthesis and testing reversible logic circuits are very important issues in this area. Multipliers are very essential for the construction of various computational units of a quantum computer. Multiplier is an important hardware unit that decides the speed in any processor. In this work, an unsigned four bit array multiplier and signed Baugh-Wooley multiplier circuits using reversible gates are implemented. A reversible Built In Logic Block Observer (BILBO) is also designed by using which the proposed reversible multiplier circuits are tested for Stuck-at faults (SAF) and missing gate faults (MGF) based on signature analysis.Design and FPGA implementation of improved lifting scheme based DWT for OFDM systems
http://dl-live.theiet.org/content/conferences/10.1049/ic.2011.0076
In this paper we present the design and FPGA implementation of improved Lifting Scheme based DWT for OFDM Systems. A generic Wavelet based DWT-OFDM for wireless communication is modeled in Simulink for various modulation schemes and wavelets, and analyzed for its BER performances and functionality and compared with Fourier based OFDM (FFT-OFDM) under AWGN Channel. For FPGA implementation of DWT-OFDM. Lifting Scheme architecture is used. Lifting based DWT architecture is better than convolution based DWT architecture in terms of area, power and speed performances. The proposed architecture is modelled using Verilog HDL and verified for its functionality in ModelSim and implemented targeting Virtex-5 FPGA development kit. The estimated frequency of operation of the design is 69.789 MHz, area is 20% of total available area and total power of 1.87907W.VHDL implementation of BIST controller
http://dl-live.theiet.org/content/conferences/10.1049/ic.2011.0077
Built-in self-test (BIST) is a design technique that allows a circuit to test itself It is a set of structured-test techniques for combinational and sequential logic, memories, multipliers and other embedded logic blocks. The principle is to generate test vectors, apply them to the circuit under test or device under test, and then verify the response. Being an automated testing, BIST enables testing at high speed and high fault coverage. BIST controller coordinates the operations of different blocks of the BIST. Based on the test mode(TM) input to the controller, the system either operates in the normal mode or in the test mode. In this paper we explain an implementation of a restart able logic BIST controller for a combinational logic circuit using VHDL. It allows us to suspend the signature generation at any desired point in the test sequence. In this case, the BIST circuit is considered to comprise hold logic and a signature generation element. The hold logic will be implemented such that an external signal (HOED) can temporarily suspend signature generation in the signature generation element at specified times during the BIST session.Eigen values and vectors computations on VIRTEX-5 FPGA platform cyclic Jacobi's algorithm using systolic array architecture
http://dl-live.theiet.org/content/conferences/10.1049/ic.2011.0044
The parallel iterative algorithms are the major advancements in the field of computing. These algorithms lead to efficient usage of hardware as well as obtaining faster results. In this paper, we describe architecture to compute eigen values and eigen vectors of a matrix having dimensions up to 50 × 50 using cyclic Jacobi's Algorithm. Systolic array architecture is used to apply it to matrices of larger dimensions. We have implemented the architecture on FPGA Vertex-5 that takes about 8059 LUT slices out of 69120 slices for matrices of dimensions 50 × 50.Secure scan design with isomorphic registers
http://dl-live.theiet.org/content/conferences/10.1049/ic.2011.0052
In this paper, we first introduce Isomorphic Redundancy concept. Two functionally equivalent shift registers can be Isomorphic to each other. They can be equivalent to each other by simple permutation of states m state tables. Two Isomorphically redundant circuits can be used to prevent two bit change insertion attack. In, addition we also propose a new model with the help of functionally equivalent shift registers. It is highly non-linear and scan-secure model.FPGA realization of spectrum sensing based on Bayesian framework for cognitive radio network
http://dl-live.theiet.org/content/conferences/10.1049/ic.2011.0043
In this paper, spectrum sensing is based on Energy detection in the frequency domain with Bayesian criterion. The sensing performance is analyzed using Monte-Carlo methods. In practice, the performance of the single node degrades due to noise effects in the channel such as fading, shadowing, and the receiver uncertainty. So, we have mitigated these effects using cooperative sensing and compare the results with single node. The simulation result discloses that the proposed detection algorithm can detect noisy signals of signal to noise ratio (SNR) up to -21dB using single node, -26dB using five nodes in cooperation at required probability of detection and false alarm probability (P<sub xmlns="http://pub2web.metastore.ingenta.com/ns/">d</sub> 0.9 and P<sub xmlns="http://pub2web.metastore.ingenta.com/ns/">f</sub> 0.1). The single node sensing algorithm is also implemented in Virtex-4 (XC4VSX35-FFG668-10) Field Programmable Gate Array (FPGA).Design and implementation of efficient multiplier using Vedic mathematics
http://dl-live.theiet.org/content/conferences/10.1049/ic.2011.0071
Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate(MAC) and inner product are among some of the frequently used computation Intensive Arithmetic Functions(CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors m its arithmetic and logic unit. Since multiplication dominates the execution tune of most DSP algorithms, so there is a need of high speed multiplier. Currently, multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications . One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. Employing this technique in the computation algorithms will reduce the complexity, execution time, power etc. This vedic based multiplier is compared with binary multiplier(partial products method).Reversible masking: a novel fault-diagnosed
http://dl-live.theiet.org/content/conferences/10.1049/ic.2011.0053
This paper suggests a novel design of reversible masking circuit for Quantum Cryptography. Quantum computation uses quantum properties to represent data and perform reversible operations on data. In this paper, we proposed to design a reversible masking logic and implement the masking logic using basic quantum gates. The masking expression is thus transformed into a Positive Polarity Reed Muller Expression to calculate its nonlinearity. We also proposed a novel quantum gate design, namely M-gate. based on the basic quantum gates. To analyze the design quantum cost is calculated can improve the circuit comparatively another masking circuit. From this circuit we are getting high nonlinearity which is much better than another masking circuit. Here also we test the circuit by using single Missing Gate Fault Model and Multiple Missing Gate Fault Model.An FPGA-based MIMO-OFDM with golden decoding
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0908
With the development of communication technology, the rising interest in wireless communication for providing mobile as well as nomadic and fixed services for video, voice and data, a new system of MIMO-OFDM is designed for providing best-in-class performance attributes such as latency, capacity, peak and sustained data rates and corresponding spectral efficiencies, overall network complexity and quality-of service management. In this paper, we present a prototype FPGA design for an available Golden decoding implementation of a MIMO-OFDM technique. Some necessary concepts of MIMO-OFDM system which are involved in the Golden decoding are introduced. The module of Golden decoding is integrated and synthesized on Xilinx, Virtex5-XC5VSX95T FPGA. The simulation and debugging tool of Modelsim is used to verify the functionality of the Golden decoding module, the simulator analysis of ChipScope and the graph of constellation of 16QAM demapping are used to analyze the captured data.A spatial hierarchy FPGA implementation with DPR square root partitions
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0904
The customized hardware platform for spatial hierarchy construction with DPR square root partitions is validly obtained. Specialized process structures and storage structures are constructed to ensure the reutilization of presorting results on each level. The objective functions for division evaluation oriented to specific applications are scheduled. DPR partitions are built to meet intensive square root finding requests. After optimizations for algorithm and architecture, such achievement provides the starting points for future development.Low power synchronous counter using improvised conditional capture flip-flop
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0429
An 8 bit synchronous counter is designed using the improvised Clock Gated Conditional Capture Flip-Flop (CGCCFF). The Conditional Capture Flip-Flop (CCFF) outputs the data, only when the input differs from the output. But, it has redundant transitions due to continuous clock flow irrespective of the input and output logic levels. The clock gating allows the clock, only when there is a need for change in output due to a change in the input. Using, the improvised CGCCFF and hence, avoiding the redundant transitions, we observe a power saving of up to 75% compared to the conventional CCFF. Moreover, it achieves a 60% higher performance than the CCFF and a better negative setup time. Hence, we implement an 8 bit synchronous counter using the CGCC flip flop. From the experimental results, we observe that, the 8 synchronous counter with CGCCFF saves 15% power than conventional CCFF counter. We simulated the results using HSPICE in 0.18μm technology.Research on time synchronization of Class B LXI bus
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0858
Based on the introduction of developments of LXI instruments, LXI instrument synchronization problem and triggering principle of IEEE1588, the causes of the synchronization are analyzed. A new synchronization algorithm of frequency compensation is proposed. The algorithm is effective in dynamic compensation. It is suggested that the algorithm should be implemented with FPGA device. With Quatus II, the dynamic compensation of the local clock is simulated and its validation is proved in the experiments. Finally the hardware implement of the whole system scheme with the dynamic compensation algorithm is proposed.The design of RS (255,239) encoder based on ADSL
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0726
The design of RS (255,239) encoder based on ADSL system GF (2 8) is studied, the core encoder multiplier unit and limited domain constant realization of hardware are presented in the paper. Because the coding process adopts 16 dedicated constant multiplier units, with variable comparison multiplier unit using before, which greatly simplified the hardware structure of multiplier unit, saved the hardware area, and improved the speed of multiplier unit. In addition, the performance of RS (255,239) coding is validated using the MATLAB programming language.Implementation of extended Kalman filter on FPGA
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0803
The purpose of this paper is to explore the concepts and consequences of implementing the Extended Kalman Filter (EKF) on the FPGA. The methods of Runge-Kutta and Taylor-Heun are applied to approximate the continuous time update. The methods of Rugge-Kutta and Gauss-Legendre are used to solve the Riccati equation in order to update the discrete time measurement. The simulation on Matlab Simulink and implementation on the hardware in-loop are completed. Tradeoff between clock frequency, hardware resources and design accuracy are analyzed in the design. Recommended works describe the limitation of the design and give the suggestion on how to save the hardware resources and increase the accuracy.Design and implementation of IEEE 802.16 baseband system on FPGA
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0794
In this paper, a physical-layer baseband modem is discussed based on IEEE 802.16 protocol. It is implemented on Xilinx FPGA and tested correctly in loop-mode. After channel coding, a bit stream goes through constellation mapper, pilot inserting, OFDM(Orthogonal Frequency Division Multiplexing) modulation, PAPR(Peak to Average Power Ratio) reduction and framing module to become 7 symbols in IQ parallel form prepared for RF(Radio Frequency) front end. On condition of loop-mode, these symbols become back to serial bit stream via synchronization, channel estimation, OFDM demodulation, pilot removing and constellation demapper in receiver part. In practice, the entire loop-mode system takes about 120us when clock rate is 40Mhz. As a consequence, the baseband system delay is much lower in order to satisfy the demands for high rate data processing in broadband communication.An independent FPGA implementation of graphical spatial hierarchy
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0323
The customized hardware platform for spatial hierarchy construction are validly obtained Mutual channels oriented to outward manipulations are established in FPGA speedup architecture for spatial hierarchical index structures Instance parameter adjusting mechanism are scheduled and constructed in the main stem of system. Multiple facilities for process and storage are built for the presorting operations. Specialized process structures and storage structures are constructed to ensure the reutilization of presorting results on each level. The objective functions for division evaluation oriented to specific applications are scheduled. Through evaluation and concatenation for the memory accessing sequences, optimized executing strategies are generated reliably to broaden the bandwidths of accessing channels. After optimizations for algorithm and architecture, such achievement provides the starting points for future development. (6 pages)Design of GPS IF signal acquisition and tracking circuits based on FPGA
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0956
This paper presents a FPGA design of a novel GPS IF signal acquisition and tracking circuits, which acquires and tracks the GPS LI frequency and C/A code without FFT and Costas loop. The suggested acquisition circuit consists of 40 branches and each of which acquires 0.5 KHz bandwidth of GPS IF signal. The tracking circuit re-acquires the GPS IF signal based on the SV number and Doppler frequency offered by the acquisition circuit and then tracks the acquired signal by means of a simple dynamic local carrier jumping method proposed in this paper instead of the traditional Costas Loop based method. A unique data demodulation technique that is suitable for the carrier jumping method is also introduced to correctly recover the modulation data. Simulation results and FPGA test show that the proposed design works well for GPS IF signal acquisition and tracking and is promising for low cost and low power FPGA applications for GPS signal processing.FPGA based high speed design for blind equalization of 8PSK signals
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0987
A high speed structure for blind equalization of 8PSK signals is presented based on FPGA. The filter section is designed with a parallel structure based on time-domain convolution. In the case of short delay spread, this structure is superior to the parallel structure based on sub-convolution filter bank in literature on computational complexity. Applying this structure to the blind equalization of 800Mbps 8PSK signals, test results show that the speed requirement is met, the hardware resources are furthest saved, and the blind equalizer converges fast.The driver design and implementation of NAND flash based on memory technology device
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0797
With the rapid development of digital technology, the application of embedded system is more and more extensive. The demand for NAND Flash storage device is growing rapidly, but the different types of embedded equipment provided by different manufacturers do not have consistent standard. So it is very important to develop the driver of NAND Flash of specific manufacturer. In this paper, the Samsung's K9G8G08U0M chip is used as an example. The fundamental structure and operational principle of NAND Flash are introduced. And then the development process of NAND Flash driver based on Memory Technology Device (MTD) is discussed in detail. The driver development process and method are very valuable for NAND flash driver of embedded equipment.A comprehensive FPGA implementation of collision detection
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0905
The customized hardware platform for collision detection is validly obtained. The components within system are spatial hierarchy constructing block, overlapping test module with pre-projection, pre- masking module for inter-objects collision detection invalidity, parameterized traversing block between geometry elements, graphical processing system on GPU platform and finally optimization block for memory accessing.. Specialized process structures and storage structures are constructed to ensure the stable operation of collision detection system.Design and implementation of a hybrid SET-CMOS based Hi-speed and power efficient pulse divider circuit
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0433
Hybrid SET-CMOS circuits which combine the merits of both the SET and CMOS promises to be a practical implementation for future low power ultra-dense VLSI/VLSI circuit design. In this work, an SET-CMOS hybrid pulse divider circuit is proposed. The MIB model for SET and BSIM4 model for CMOS are used. The operation of the proposed circuit is verified in Tanner environment. The performances of CMOS and Hybrid SET-CMOS based pulse divider circuits are compared. The hybrid SET-CMOS circuit is found to consume lesser power than the CMOS based circuit. Further it is established that hybrid SET-CMOS based circuit is much faster compared to CMOS based circuit.Future of computer hardware
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0007
Summary form only given. "Experienced prophets concerning the future." are careful with predictions With this statement in mind, in this paper recent developments in computer hardware are considered along their technical possibilities and limitations. Beyond available standard multicore CPU hardware, this involves the recent impact of specialized accelerator hardware: Currently, general purpose graphic processing units (GPGPUs) and programmable specialized hardware such as FPGA processors or e.g. IBM's Cell processor are successfully used in the field of high-performance computing. This specialized co processor technology gives rise to hybrid-type processors integrating CPU and GPUs. Upcoming candidates for such hybrid-architectures are Intel's "SandyBridge" processor architecture arising from the "Larabee" project, the upcoming systems from AMD including the graphics accelerator technology of ATI Technologies into their CPUS or the future fusion processors recently announced by the companies ARM and NVIDIA under project codename "Denver". The data-level parallelism required for these architecture to achieve suitable high-performance levels has an impact on the development and use of computational electromagnetics (CEM) algorithms and simulation tools: The required use of Single Instruction Multiple Thread (SIMT) operations on massively parallel compute-kernel structures results in a severe performance sensitivity with respect to a controlled flow of the data streams. As a result, these specialized computer architectures will favour numerical schemes which implicitly support these features. High data locality and an intrinsic parallelism usually results in a good ratio between the computational workload for the floating point units (FPUs) and the need for data movement. This can be found e.g. in higher order Discontinuous Galerkin FEM time domain formulations. More generally, discretized field formulations using explicit time integration schemes commonly are easier to parallelize than those based implicit schemes, where complicated solution schemes are required for the algebraic systems of equations involved. Beyond the currently valid paradigm of massive parallelism which follows several decades of a steady increase in the average wall-clock speed of CPU architectures, current research on computational architectures also focuses on reconfigurable systems. First systems using hybrid-core computing by CPUs with programmable FPGAs are becoming available and are already in use for data intensive applications. Future systems featuring fully reconfigurable special-purpose cores that are capable to adapt to the computational task at hand are currently under development. The possible full impact of such reconfigurable core systems to the field of computational electromagnetics is yet an open subject to speculation, although some research results on FDTD implementations hard-coded on FPGAs have been published already in the past recent years. Another important topic to be addressed with future computer hardware is the need to optimize the ratio of computational performance in relation to the electric power consumption (Flop per Watt): On a technical system level, a high electric power density is cause for concern because of resulting thermal stresses and often results in the need for expensive cooling measures. On a macroscopic economical level, the costs of the electric energy consumption of the computer system itself and its external cooling systems result in increasing total costs of ownership (TCO). With an increasing need for very large scale CEM computations e.g. in computational electromagnetic compatibility testing, these TCO costs are no longer negligible even for medium scale compute-clusters in an industrial or research environment. In addition, the reduction of electric energy consumption of the compute cores is an essential technical necessity in the design of future high-performance computer systems in the exa-flop scale. With these future super computers to be available approximately in 2018 (following Moore's law) the contemporary peta-flop super computers are to be exceeded in terms of computational performance by three orders magnitude, but they may not so exceed these in terms of electric energy consumption.A FPGA ray tracing scheme with memory optimization facility
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0903
This article presents a ray tracing acceleration system realized on FPGA platform. Additionally we make improvement to the memory accessing performance and achieve ideal ratio of performance against resources. Such work will gain ray tracing more applicable regions. The global scheme includes spatial indexing hierarchy module, ray generation module, pre-masking module, packet traversal module, arithmetic module and memory optimization facility which is described specially in this article..Design and implementation of Kalman filter
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0800
Kalman filter is used in the high rate low-pass filter due to its simple architecture. This paper analyzes the performance of the Kalman filter based on the setting time and amplitude-frequency response, which is significant to the design of Kalman filter. Then this paper proposes a new method of shift operation instead of the original one, which solves the loss of data caused by the original shift operation. The result of the implementation and simulation based on FPGA shows that the proposed method can avoid loss of data.Power system restoration using reverse delete algorithm implemented in FPGA
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0392
A graph theory based algorithm called as reverse delete algorithm to find the optimal path of power flow for a given network is proposed in this paper. Whenever an outage occurs in the distribution network, the power has to be restored to the isolated area by altering the path of power flow, which is achieved by altering the switching positions of the network. The reverse delete algorithm helps in finding the path of least impedance called minimum spanning tree to supply the power to the isolated areas. Backward sweeper based load flow technique is applied to this resultant minimum spanning tree. Based on the results (voltage, current and power flow) obtained from the load flow solutions, other constraints of the restoration problem are applied. The results are tabulated for 33 bus single feeder distribution network and for 16 bus multi feeder distribution network. The hardware implementation of this algorithm is done using Verilog HDL.A low power multiplier architecture based on bypassing technique for digital filter
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0432
The objective of the paper is to present a low power 4×4 digital multiplier design to reduce power consumption of digital multiplier based on 2-dimensional bypassing method. Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. The proposed bypass cells constitute the multiplier skip redundant signal transitions when the horizontally partial product or the vertical operand is zero. Hence, it is a 2-dimensional bypassing architecture using which we designed a Digital filter for low power dissipation in signal processing applications. Thorough post-layout simulations show that the power dissipation of the proposed 2D multiplier and FIR filter design based on 2D multiplier is reduced by more than 75% compared to the prior design with obscure cost of delay and area.Designed and implemented of graphics rasterization algorithm with FPGA
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0902
The rasterization stage, which is an important part of a graphics processing unit, always requires huge operations and is the bottleneck of the performance, especially for mobile devices. In this paper, the authors research the rasterization algorithm and optimize some rasterization algorithm. In the last, the authors implement a simple rasterization engine with small hardware resource of FPGA.FPGA implementation of hot spot detection in infrared video
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0518
This paper describes a Hardware Description Language (HDL) based fully customizable module for real-time Infrared (IR) hot spot detection and feature extraction from a video stream. The aim of the research was to investigate and evaluate possible solutions for object detection using connected component labelling that could be implemented within a streaming video embedded processing platform as a hardware accelerator. The proposed algorithm is based on a single-pass approach; this guarantees real-time processing together with very low resource utilisation. The hardware implementation was verified on a Xilinx XUP V2P (XC2VP30 FPGA) development board with an IR camera module interfaced as a real-time video source. The system was tested with an image resolution of 640 × 480 processing input data at a speed of 30fps which was limited by the bandwidth of the camera.The impact of neural model resolution on hardware spiking neural network behaviour
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0515
This paper contributes to the development of the proposed EMBRACE mixed-signal, reconfigurable, Network-on-Chip based hardware Spiking Neural Network. EMBRACE-FPGA is an FPGA-based prototype of the proposed EMBRACE architecture. Results from successful evolution of an EMBRACE-FPGA SNN robotics controller are presented. Noise in best fitness plots for a range of evolved EMBRACE-FPGA based SNN applications, including the robotics controller, have been observed. This paper investigates the sources of neural noise, and considers their impact in evolving digital-based hardware SNNs. The paper considers the expected performance benefits of the EMBRACE analogue neural cell.Experimental demonstration of optical processor-memory interconnection
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0755
In this work, we experimentally demonstrated the feasibility and performance of an optically-connected processor-memory system. An emulated CPU with the on-chip memory controller was implemented on a high-speed FPGA evaluation board, which communicated with another SRAM module through independent Rocket IO transceivers connected by a 2.5 Gb/s optical channel. Data integrity and error-free performance are verified with a sequence of SRAM write and read operations.FPGA based high accuracy optical flow algorithm
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0497
Motion estimation of a scene is an interesting problem in computer vision since it is the basis for the dynamic analysis of a scene. However this task is computationally intensive for conventional processors. In this work, an FPGA-based hardware architecture for real-time motion estimation is proposed. The algorithm implemented in hardware is a gradient based inverse finite element method for optical flow computation. It manages the motion estimation of the image by calculating the Gradient, Laplacian, and Velocities of each pixel in a parallel design which improves computational speed. The algorithm used in this paper has been benchmarked against many of the well known algorithms and shows superior performance in terms of average angular error and standard deviation. The FPGA design is presented with preliminary results and discussed.Design and implementation of a SoC-based security coprocessor and program protection mechanism for WSN
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.1044
The practical applications of wireless sensor networks in vulnerable areas require the communication data of sensor devices confidentiality, integrity and freshness. Furthermore the program data of sensor devices need to be protected. In this paper, we present the design, implementation and simulation of an effective hardware security coprocessor namely RC5-FKM and program protection mechanism based on system on chip (SoC) technology for wireless sensor networks (WSN). Compared with existing works, the unique features of our design includes: (1) a design of fingerprint based key management (FKM) is implemented in SoC, which is used to build secret keys for cryptographic coprocessor. (2) A program protection mechanism is proposed to prevent the program data from being read out by system intruders so as to improve the security of program data in sensor device. (3) A reusable optimized logic cell (ROTL) including some adders and registers is implemented in RC5-FKM, which results in the elimination or minimization of the additional hardware overhead. The design is mapped on FPGA and ASIC design. Results show that the hardware overhead of our design is 9.6% less than previous designs and the execution time of our hardware design is only 0.2% of that of general processors and shorter than other AES coprocessors.VHDL guidance for safe and certifiable FPGA design
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0832
Field Programmable Gate Arrays (FPGAs) are becoming increasingly popular for use within high integrity and safety critical systems. One commonly used coding language for their configuration is the VHSIC Hardware Description Language (VHDL). Whilst VHDL is used for hardware description, it is developed in a similar way to traditional software, and many safety critical software certification standards require the use of coding subsets and style guidance in order to ensure known language vulnerabilities are avoided. At present there is no recognized, public domain guidance for VHDL. This paper draws together many different sources to provide a starting discussion for a VHDL subset. (6 pages)A configurable FFT Processor
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0662
In this paper, a configurable FFT processor is presented which can be configured as 8192 point, 4096 point, 2048 point and 1024 point FFT processor. The processor is based on mixed radix algorithm and single-path delay feedback(SDF) architecture is adopted. The configurable architecture is achieved by connecting or bypassing specific processing elements. To improve processor performance, a dynamic scaling approach is adopted and internal data is formatted as self-defined floating point, and the arithmetic for the self-defined floating point is simple. The experiment results show that the approach can achieve high and constant SNR. The processor is implemented on FPGA.A hardware wrapper for the SHA-3 hash algorithms
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0478
The second round of the NIST public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). Computational efficiency of the algorithms in hardware is to be addressed during the second round of the contest. For software implementations NIST specifies an application programming interface (API) along with reference implementation for each of the designs, thereby enabling quick and easy comparison and testing on software platforms, however no such specification was given for hardware analysis. In this paper we present a hardware wrapper interface which attempts to encompass all the competition entries (and indeed, hash algorithms in general) across any number of both FPGA and ASIC hardware platforms. This interface comprises communications and padding, and attempts to standardise the hashing algorithms to allow accurate and fair area, timing and power measurement between the different designs.Synchronization technology for OFDM system and its FPGA design
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0660
For one of the focus communication technology, Multicarrier modulation OFDM (Orthogonal Frequency Division Multiplexing), this paper, based on the previous study of basic modem module, carry out some research on its key synchronization technology. The key point includes adding cyclic prefix and suffix to reduce requirement on accuracy of symbol synchronization, FFT window synchronization time and adding the training sequence to extract bit synchronization signal . In our subject study, algorithm is researched based on MATLAB language. And also introduces several considerations in FPGA circuit Hardware implementation.Synthesis of glue logic, transactors, multiplexors and serialisors from protocol specifications
http://dl-live.theiet.org/content/conferences/10.1049/ic.2010.0148
Today's system-on-chip (SoC) systems must be designed as quickly as possible by integrating IP blocks from diverse suppliers. In this paper, we present a new automata based algorithm that automatically synthesizes glue logic for SoC fabrication and Transaction-level modelling (TLM) transactors for SoC modelling. Our approach introduces a new encoding for state variables which captures data conservation property and supports simple point-to-point connections as well as those the perform functions such as multiplexing, filtering and serialising.FPGA-based generalized scalar pulse-width-modulation for matrix converters
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0001
This paper presents an entire FPGA implementation of a modulation technique for matrix converter known as Double-Sided Generalized Scalar Pulse Width Modulation. The main advantage of this technique is the possibility to emulate the behaviour of many modulation techniques, including the wellknown Space Vector Modulation. Due to the absence of complex algebraic and trigonometric operations in the generalized modulation technique, it is possible to implement the entire control system of the matrix converter in a single FPGA chip. Simulations and experimental results show the effectiveness of the implementation. (6 pages)Sliding mode observation of capacitor voltage in multilevel power converters
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0014
In this paper a sliding mode observer is designed and applied to a two-port multi-cellular power converter topology in order to observe the DC-link capacitor voltages. Among different sliding mode observers, the Sliding Mode Observer (SMO) using equivalent control approach has been selected for use because of its robustness against uncertainties in system equations. Simulation is carried out using SABER software. For practical results the controller is implemented on a TMS320C6713 DSP and two ACTEL FPGAs. The observer equations are implemented on an FPGA using a fixed-point system programmed in VHDL. (6 pages)Tiny-π: a novel formal method for specification. Analysis, and verification of dynamic partial reconfiguration processes
http://dl-live.theiet.org/content/conferences/10.1049/ic.2010.0134
On FPGA-platforms, the feature of dynamic partial reconfiguration offers a wide range of applications. We propose a new formal method for design, analysis, and verification of the reconfiguration process on such devices. The π-calculus, also known as the calculus of mobile processes, is a type of process algebra typically used to describe dynamic communicating processes. We propose the π-calculus as a foundation to model dynamic partial reconfiguration of hardware modules. A subset of this calculus that we call tiny-π can be executed in resource restricted, embedded environments which feature reconfiguration properties. As a proof-of-concept, we present a small virtual machine implementation for tiny-π. We have also implemented a compilation flow from a textual description of tiny-π specifications into executable bytecode. The virtual machine, running on an embedded Microblaze processor on an FPGA, can execute the bytecode and trigger corresponding reconfiguration commands for a dynamically reconflgurable FPGA platform.A matrix converter control embedded in a single system on chip based on a FPGA
http://dl-live.theiet.org/content/conferences/10.1049/cp.2010.0206
The matrix converter (MC) presents a promising topology that needs to overcome certain barriers (complexity of the modulation and control techniques, protection systems, etc.) in order to gain a foothold in the industry. This article deals with the implementation of the DS SVM vector modulation, commutation and protection of the MC through a series of hardware blocks (cores) integrally implemented in an FPGA. Likewise, given that all the processing capabilities have been integrated in a single chip, it can be said that an FPGA-based System on a Chip (SoC) has been designed. (6 pages)Formal verification of timed VHDL programs
http://dl-live.theiet.org/content/conferences/10.1049/ic.2010.0133
The verification of timed digital circuits is an important issue. These circuits are composed by logical gates, each of them being associated with propagation delays. The analysis of such circuits is necessary to identify critical path and adjust the clock period of the circuit or to determine the stability period of input/ouput signals. These circuits are represented by a functional model described in VHDL and a timing model associating propagation delays to each functional block. This model is translated into timed automata formalism upon which classical simulation or model checking verification can be performed. This method rises two problems: 1) Propagation delays associated to a gate depend on the transistor assembly and the manufacturer's technology. How do we associate propagation delays to a logical gate ? 2) How to automatically translate a VHDL functional description, combined with propagation delays, into timed automata ? This paper addresses these two problems. It presents a method automating the verification of VHDL descriptions, augmented with interval bounded propagation delays, obtained by electrical simulation of the transistor model of the gates.FPGA implementation of SNR estimation for DSSS signal of space borne secondary radar
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.0483
According to the problem of SNR estimation for DSSS signal in space borne secondary radar, an efficient approach has been presented. For the implementation of real-time processing of SNR estimation, the efficiency is improved by the redesign of the algorithm flow. Moreover, the SNR estimation is accomplished on a large-scale programmable gate array with the capability of processing high resolution. Simulation results indicate that the principle of the method is correct. Taking into account the space condition, the method performs well. (4 pages)The MOD procurement guidance on software safety assurance assessing and understanding software evidence
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.1547
The UK Ministry of Defence (MOD) has compiled acquisition guidance for the safety of systems containing complex electronic elements (CEEs) to complement Def Stan 00-56 Issue 4. The term CEE is defined in the Def Stan and refers to both software and custom hardware, this means that terms such as firmware become redundant from a standards perspective. CEE also encompasses the development processes of Field Programmable Gate Arrays (FPGAs) which are treated the same as software. The MOD Guidance is applicable to any acquisition project whose CEE has any effect on the safety of the overall system. This paper outlines the strategy and key points of the Guidance. Throughout the paper the term CEE and software are interchanged as they are viewed, from a safety and standards perspective, as the same problem. (12 pages)Implementation of two dimensional pulse compression based on embedded processor in FPGA
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.0131
This paper first analyses the technology characteristic of FPGA. An efficient two dimensional pulse compression processing system in which FPGA is the platform of signal processing and its embedded processor MicroBlaze is control kernel is designed and implemented using Xilinx's XC2V6000FPGA. In the limit of resource in FPGA, two different implementation architectures of pulse compression are presented in terms of speed and area restrictions. A DDR SDRAM controller which is realized in FPGA carries out efficient matrix transposition processing under the way of matrix partition linear mapping. Further more, a simple SAR imaging processing is simulated in this FPGA system for validation. (4 pages)Iris image quality assessment based on FPGA coprocessor
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.2013
The quality of iris image is a key point to affect the accuracy of iris recognition system. There are four main abnormities of captured iris image: defocus, motion blur, eyelid occlusion and eyelash occlusion. They can be distinguished by comparing different frequency components of the image. This paper describes a technique of using Field Programmable Gate Arrays (FPGA) coprocessor to assess the quality of the iris image in a Texas Instrument (TI) Digital Signal Processor (DSP) based Iris Recognition System, by implementing Laplacian Sharpening and 2D-FET transform on the chip. FPGA has become an extremely cost-effective mean of computing algorithms to improve system performance and enhance the computation capability and flexibility of the iris recognition system based on DSP.