New Publications are available for Computer-aided circuit analysis and design
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New Publications are available now online for this publication.
Please follow the links to view the publication.A 16nm SRAM design for low power and high read stability
http://dl-live.theiet.org/content/conferences/10.1049/ic.2011.0045
SRAM memory design in nanoscale regime has become increasingly challenging due to the reducing noise margins and increased sensitivity to threshold voltage variations. To overcome these challenges, different memory cells have been proposed for SRAMs with different transistor structures. These designs improve the cell stability in the subthreshold regime but suffer from bitline leakage noise, placing constraints on the number of cells shared by each bitline. In this paper, we propose a novel 11T SRAM cell topology which achieves cell stability as well as prevents bitline leakage. In addition to that, the proposed cell shows appreciable improvement in the dynamic power consumption. The HSPICE simulation and analysis at a 16nm feature size in CMOS process shows that the bitline leakage power consumption of the proposed 11T SRAM cell is reduced by 38% and the dynamic power consumption is reduced by 54% when compared to the existing 10T SRAM cell, while maintaining the read static noise margin nearly twice that of conventional 6T SRAM circuit.Low power synchronous counter using improvised conditional capture flip-flop
http://dl-live.theiet.org/content/conferences/10.1049/cp.2011.0429
An 8 bit synchronous counter is designed using the improvised Clock Gated Conditional Capture Flip-Flop (CGCCFF). The Conditional Capture Flip-Flop (CCFF) outputs the data, only when the input differs from the output. But, it has redundant transitions due to continuous clock flow irrespective of the input and output logic levels. The clock gating allows the clock, only when there is a need for change in output due to a change in the input. Using, the improvised CGCCFF and hence, avoiding the redundant transitions, we observe a power saving of up to 75% compared to the conventional CCFF. Moreover, it achieves a 60% higher performance than the CCFF and a better negative setup time. Hence, we implement an 8 bit synchronous counter using the CGCC flip flop. From the experimental results, we observe that, the 8 synchronous counter with CGCCFF saves 15% power than conventional CCFF counter. We simulated the results using HSPICE in 0.18μm technology.Co-simulation tuning methods for lumped element filters
http://dl-live.theiet.org/content/conferences/10.1049/ic.2010.0177
With the advent of higher speed communication links comes the requirement for ever wider link bandwidths. Channel filtering provides a critical part of any up-converter or down-converter. A typical down-converter encapsulates an Image Filter, a mixer, several Amplifiers, and baseband channel filtering, typically at frequencies less than 500MHz. Traditional high-loss transversal SAW filters are typically used, but can now be replaced with an alternative approach using lumped element technology. These offer many advantages to SAW filters, including low loss, excellent thermal stability, improved stopband rejection, and wideband filtering at low centre frequencies (>30%). This paper discusses the constraints on complex lumped element filter design and realisation, and demonstrates how these difficulties can be overcome with a novel co-simulation technique with a practical example using PCB technology.Genetic-based high-level synthesis of ΣΔ modulator in SystemC-A
http://dl-live.theiet.org/content/conferences/10.1049/ic.2010.0147
This paper proposes a novel genetic-based high-level synthesis methodology for ΣΔ modulators. This approach is based on simulation-based optimisation where optimal topology of the ΣΔ modulator is automated explored using a genetic algo rithm(GA) under various design constraints, such as SNR(Signal to-Noise Ratio) and hardware complexity. The proposed synthesis technique has been implemented in SystemC-A due to its ad vantages in terms of high simulation speed, flexibility and data manipulation. Experimental results validates the effectiveness of the synthesis approach.An accelerated mixed-signal simulation Kernel for SystemC
http://dl-live.theiet.org/content/conferences/10.1049/ic.2010.0158
Mixed-signal system simulation often lacks either performance or accuracy. We attempt to bridge the gap between abstract digital models and analog netlists by performing an accelerated mixed-level transient simulation. A precomputation method at electrical level allows for a considerably faster simulation than with SPICE like simulators. Utilizing an automatically generated SystemC interface, our simulation kernel analyzes mixed analog/digital circuits where mixed-level digital descriptions are possible. Results show a speedup of up to two orders of magnitude compared to mixed-signal simulation using ModelSim coupled with Saber or HSpice.Simulation design of submillimeter wave subharmonic mixer
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.1308
This paper introduces the circuit simulation design of a submillimeter wave subharmonic mixer. Detailed simulation design procedures of mixer diodes, transition, filter and matching circuits are depicted. The mixer using commercially available DBES105a GaAs Schottky barrier diodes is designed to operate in an RF frequency of 361 GHz when supplied with a LO frequency of 180 GHz. The result of simulation shows that the conversion loss of the mixer is less than 15 dB in an RF frequency from 357.5 GHz to 362.5 GHz with a LO power of 6 dBm.Investigation of crosstalk between wires using PEEC
http://dl-live.theiet.org/content/conferences/10.1049/cp.2009.1289
The existence of parasitical parameters, such as coupling inductances and coupling capacitance between wires, makes crosstalk inevitable. In order to investigate the effect of crosstalk, accurately and efficiently computing of parasitical parameters is needed. In this paper, Partial element equivalent circuit (PEEC) method is used to partition the model of wires and ground plane, to extract the partial parameters of resistances, capacitances and inductances forming the equivalent SPICE circuit and to analyze the effect of crosstalk. Different kinds of relative position of wires are considered.An accurate large-signal model for RF SOI LDMOS including self-heating effect
http://dl-live.theiet.org/content/conferences/10.1049/cp_20080796
An accurate RF SOI LDMOS large-signal equivalent circuit model based on NXP MOS Model 20 (MM20) is presented. The avalanche effect and the power dissipation caused by self-heating are described. The RF parasitic elements are extracted directly from measured S-parameters with analytical methods. Then their final values are obtained quickly and accurately through necessary optimization. The model is validated in DC, AC small-signal, and large-signal analyses for an RF SOI LDMOS of 20-fingers (channel mask length, <i xmlns="http://pub2web.metastore.ingenta.com/ns/">L</i> = 1μm, finger width, <i xmlns="http://pub2web.metastore.ingenta.com/ns/">W</i> = 50 μm) gate with high resistivity substrate and body-contact. Excellent agreement is achieved between simulated and measured results for DC, S-parameters (10 MHz~20.01 GHz), and power characteristics, which shows our model is accurate and reliable. MM20 is improved for RF SOI LDMOS large-signal applications. This model has been implemented in Verilog-A using the ADS circuit simulator (hpeesofsim).Three-dimensional parallel FDTD simulation of light-emitting diodes
http://dl-live.theiet.org/content/conferences/10.1049/cp_20080231
Three-dimensional FDTD simulation of light-emitting diodes is undertaken with the use of a high-performance parallel computing cluster. It is envisaged that much larger structures was simulated resulting in an improved design process for emission enhancing structures.Circuit fault & failure description language
http://dl-live.theiet.org/content/conferences/10.1049/cp_20080701
In this paper, we aim at formalising an experimental fault and failure description language in order to design a safety verification process for circuits. We would like to extend methods and techniques which check that circuits are design fault free, e.g. they correctly behave in normal mode, in such a way that circuits could be statically verified as well when unexpected failures arise, e.g. in degraded mode. We then model a formal fault and failure description language that suits a tiny language able to design structural configuration of circuits. As we borrow Gordon and Melham's "circuits as predicates" paradigm to perform circuit design verification, we shall define fault and failure semantics in terms of "predicates transformers". We choose to take advantage of higher order logic features to realise this goal. Then we are able to build a verification process for safety properties that express the conditions from which circuit behaviour can be proved stable when faults and failures arise. (5 pages)Comparison of Euclidean distance based neural networks for analog integrated circuits fault recognition- LVQS &SOM
http://dl-live.theiet.org/content/conferences/10.1049/ic_20070676
The advent of integrated circuits (ICs) and hence the subsequent miniaturization of electronic circuitry has brought out considerable difficulties encountered during identification of faults in integrated circuits during the testing phase of manufacturing and subsequent mass production. Artificial neural network (ANN) augurs well in handling such complex tasks in such systems as it generalizes well without the need to explicitly define the relationship between variables. There has been resurgence in interest among researchers in utilizing ANN for recognizing faults in analog circuits. This work aims at analyzing the role played by the various training parts of both the Euclidean distance based ANNs namely, the self organizing feature maps(SOM) and various versions of learning vector quantization neural network (LVQNN)i.e., LVQ1, LVQ 2, LVQ 2.1 and LVQ. Extensive studies have been conducted to ascertain the role played by learning rate and other unique parameters such as the role played by normalization as a part of preprocessing technique and the number of iterations for convergence. Moreover the results have been compared with the generalized multilayer feedforward network with back propagation algorithm. The best combination of network parameters was also determined. For this purpose an analog filter circuit with 1 fault free and 10 single hard faults was simulated using SPICE simulation software. Experimental results demonstrate the high classification accuracy and the adaptability of both the Euclidean classifiers and its suitability for fault recognition in analog circuits.Closed loop CLL type AC/DC converter using ORCAD PSPICE
http://dl-live.theiet.org/content/conferences/10.1049/ic_20070607
The closed loop CLL type converter system does AC/DC conversion with high power density. This is possible by using smaller size filters. Low frequency AC is converted into DC an using uncontrolled rectifier. This DC is converted into high frequency AC using MOSFET inverter. The filter size is reduced since the MOSFET inverter operates at high frequency. This AC is converted into DC by using a rectifier at the output. The size of the capacitor filter will be reduced since the ripple frequency is very high. The waveforms are simulated using PSPICE. The harmonics are studied using Fourier transform. This converter is used for defence power supplies and aircraft power supplies.Circuit model simulation for separate absorption, grading and multiplication avalanche photodiodes (SAGM-APD) considering gradual changes of the electric field in active region
http://dl-live.theiet.org/content/conferences/10.1049/ic_20070732
In this paper, we obtain a circuit model for separate absorption, grading and multiplication avalanche photodiodes (SAGM-APD). In this circuit modelling we consider the gradual changes of electric field in active region using split- step method . This circuit model is based on the carrier rate equations in the different regions of the device. Using the model we obtain the quantum efficiency and dark current. As examples, InP/InGaAsP/InGaAs SAGM-APD is simulated. There is a good agreement between the simulation and experimental results.VLSI design and implementation of INTEL 8253IC using VHDL
http://dl-live.theiet.org/content/conferences/10.1049/ic_20070727
VLSI technology allows a designer to implement a complex design in software and perform a series of simulation on it, before sending the design for actual fabrication. Hence the time involved in testing the design is reduced. Any error would enable the designer to make changes in the design, rate it on the simulator before sending it for fabrication, thus reducing error. The design is specified to the simulator in various ways. In this paper a popular method is used, a hardware description language VHDL designs technique to implement the entire functionality of the INTEL 8253 programmable interval timer.An algorithm for electronic circuit solution using MATLAB
http://dl-live.theiet.org/content/conferences/10.1049/ic_20070694
In this paper an algorithm for electronic circuit solution using MATLAB is proposed. The given electronic circuit consisting active elements observes the nonlinearity. So first the circuit equations are linearised by converting the active elements e.g transistors into diodes and other resistive elements by Eber's-moll model (Millman and Halkias). The resulting linear simultaneous equations are solved for computing the values for various voltages using MATLAB. These features make the proposed algorithm as the basis for AC analysis of very large electronic circuits.Hearing aid: a current mode approach
http://dl-live.theiet.org/content/conferences/10.1049/ic_20070673
The design of a current mode resistorless continuous time biquadratic filter for hearing aid application employing CCCIIs is presented. The circuit is capable of amplifying or attenuating signal at one or more selective band(s) of frequencies within the whole audio spectrum. The proposed circuit uses minimum number of active and passive elements. The electronic controllability of the filter parameters is achieved by bias currents of CCCIIs. PSPICE simulation results are shown to validate the theoretical results.A new large-signal model of RF-LDMOSFET on SOI
http://dl-live.theiet.org/content/conferences/10.1049/cp_20070736
This paper presents a new large-signal model of RF-LDMOSFET with body-contact on SOI, amenable for integration into commercial nonlinear simulators. A new continuous and derivable empirical channel current model is proposed, which can represent drain conductance and trans-conductance characteristics accurately. An enhanced charge-conservative model is proposed. The predictive model capabilities are illustrated with measured and simulated DC characteristics, S-parameters, fundamental, 2nd and 3rd harmonics power data of a RF-LDMOSFET on high resistivity SOI. The nonlinear simulation is implemented in Agilent technology ADS2005A using Verilog-A(AMS) language.Steady-state and transient electro-thermal simulation of power devices and MMICs based on 3D physical thermal models
http://dl-live.theiet.org/content/conferences/10.1049/cp_20070804
Coupled electro-thermal simulations are presented to demonstrate predictive design in microwave circuits. These simulations are performed using an analytical method comparing time-dependant circuit simulator fREEDA™ with the finite element method (FEM) incorporated in COMSOL Muttiphysics™ software. A 3D physical thermal model was developed in COMSOL to model the thermalmmic element in fREEDA™. The advantages of these two packages are illustrated by comparisons of the simulation results from steady-state and transient analyses for illustrative circuits.A novel and powerful TCAD methodology to evaluate performance of ESD protection devices
http://dl-live.theiet.org/content/conferences/10.1049/cp_20070677
On-chip electrostatic discharge (ESD) protection requires not only extensive technical experience but also scientific technology computer aided design (TCAD) methodology for evaluation. A novel and powerful TCAD methodology aimed to evaluate performance of ESD protection devices objectively is developed and presented. Mix-mode transient circuit simulation, which depicts ESD events better, is acquired in this simulation method. This TCAD methodology pays more attentions to the transient behaviors and characteristics of ESD protection devices which are more valuable to predict performance of ESD protection devices. This TCAD methodology with good ability of convergence can evaluate the performance of ESD protection devices scientificly and has strong direction ability to the design of ESD protection devices.Technology Computer Aided Design for Si, SiGe and GaAs Integrated Circuits
http://dl-live.theiet.org/content/books/cs/pbcs021e
<p xmlns="http://pub2web.metastore.ingenta.com/ns/">The first book to deal with a broad spectrum of process and device design, and modelling issues related to semiconductor devices, bridging the gap between device modelling and process design using TCAD. Presents a comprehensive perspective of emerging fields and covers topics ranging from materials to fabrication, devices, modelling and applications. Aimed at research-and-development engineers and scientists involved in microelectronics technology and device design via Technology CAD, and TCAD engineers and developers.</p>Multi-goal (S-parameter, OTA, SAR) optimization of industrial mobile phones using genetic algorithms
http://dl-live.theiet.org/content/conferences/10.1049/ic.2007.1136
In recent years, full-wave numerical simulation has become an effective means to support RF engineers in the analysis and design of such devices. Nevertheless automated optimization was so far restricted to simple structures due to large number of required simulations for multi-goal optimization. This paper presents a novel approach which allows to perform the effective optimization of entire CAD derived devices, embedded in complex environments. The new optimizer combines the advantages of enhanced genetic algorithms with the unique and superior speed of FDTD hardware acceleration. On the basis of a commercial mobile phone, the applied methods are outlined and demonstrated whereas the devices' antenna is optimized with respect to return loss/matching, radiation performance and SAR under real usage conditions, i.e., including head and hand. In addition, our optimization technique runs a sensitivity study for each optimized parameter in parallel. (5 pages)Simulation technology for efficient millimeter-wave IC development
http://dl-live.theiet.org/content/conferences/10.1049/ic_20060109
Development of millimeter-wave integrated circuits - and, thus, systems at moderate cost depends strongly on circuit simulation software. The demands placed on such software by design at millimeter wavelengths are much greater than those at the lower microwave frequencies. At the same time, the relatively high cost of testing and "tweaking" millimeter circuits, their lower yield, and the need for advanced technologies, makes such software an especially critical part of a practical, low-cost design flow. This paper discusses the requirements of such software and describes the ways in which improvements in both simulation technology and basic software technology have made efficient millimeter-wave circuit design possible.Challenges for auto code generation and verification (Abstract only)
http://dl-live.theiet.org/content/conferences/10.1049/ic_20060571
In the talk, we will describe the main challenges engineers face while using design automation tools with code generators to produce ready-to-embed code. We will focus on the difficulties finding runtime errors in the generated code. These errors may be caused by scaling choices, dictionary inconsistencies or simply design issues in the model. We will finally present the PolySpace product that can be used to find most of these errors.Semiconductors + software: the fuel of the modern economy (Abstract only)
http://dl-live.theiet.org/content/conferences/10.1049/cp_20062254
Since the birth of the transistor in 1947 semiconductor technology has seen a rapid rate of development, leading to a vast diversity of applications. Today's integrated circuits can now contain up to a billion transistors and provide the fuel for the Digital Information Age which so seamlessly affects all of our lives and touches billions of people on our planet. Today's technology is "embedded" or hidden in applications such as mobile phones, digital cameras, information appliances, control systems, automotive electronics with the digital systems of today doing the work of mechanical systems of the past. The software content of many systems is now more costly than the metal out of which they are built. With the opposing forces of added complexity with increasing pressure to shorten time to market, the semiconductor industry has reached a level of maturity that has caused horizontal specialist companies to emerge with a theme of global teamwork being necessary for success. Sir Robin Saxby will give a brief history of the semiconductor industry, highlighting the new challenges and applications as we look toward 2020. He will touch on the way in which our power networks have embraced the advancement of control systems in power distribution. He will also discuss how developments in this field have given rise to more powerful yet more power efficient and lower cost devices. (1 page)Large time-scale electro-thermal simulation model of Inverter Power Module (IPM) for hybrid vehicle applications
http://dl-live.theiet.org/content/conferences/10.1049/ic_20050485
A novel electro-thermal decoupled approach for large time-scale electro-thermal simulation of an inverter power module (IPM) used to drive a permanent magnet synchronous motor (PMSM) is presented. The key assumption is that the inverter drive system electrical performance is not affected by the temperature of the semiconductor power devices; this allows the electrical and thermal simulations to be decoupled. Based on this strategy, the electro-thermal simulation of the inverter power module is divided into two phases: (1) the overall electrical simulation of the inverter drive system in the continuous time domain; (2) PWM switching signal based power losses calculation and the thermal simulation of the inverter power module. The feature of this method is that the PWM switching signal is reconstructed using continuous smooth time-domain motor voltages obtained from phase (1), so that accurate power loss calculation and thermal simulation can be carried out using continuous smooth electrical waveforms. In this way, the conventional approach where devices are represented by switches is avoided and the electrical-thermal simulation can be carried out using relatively large simulation time steps, which allows a significant speed-up of the simulation. Simulation of over 10 minutes of real time operation has been carried out; the total simulation is of the order of 1 hr CPU time for a 3.12 GHz CPU 1 Gbyte memory PC.Automating systems integration and electrical distribution in modern car platforms
http://dl-live.theiet.org/content/conferences/10.1049/ic_20050487
Growth and choice in platform electronics is now extremely challenging. Modem platforms frequently employ more than 80 separate systems, populated by hundreds of devices and thousands of electrical connections. Furthermore, the extraction of specific vehicle configurations that reflect optional content and model derivatives introduces further complexity. This paper describes a modern methodology that enables engineers to integrate participating systems efficiently. The methodology leverages a company's intellectual property via reusable rules that guide the allocation of devices into packaging locations, and subsequently synthesizes the physical wiring that supports the underlying logical connectivity.SVD image filtering on FPGA
http://dl-live.theiet.org/content/conferences/10.1049/cp_20040590
The paper presents the implementation on FPGA of a block SVD method for image denoising. This method exploits the fact that only the smallest singular values are affected by the noise and therefore can be discarded, leading to an efficient nonlinear image filtering. An efficient architecture for singular value decomposition (SVD) based on the Brent, Luk, Van Loan (BLV) systolic array has been proposed. The architecture is three times more efficient and three times faster than the existing BLV structure. An optimised implementation has been efficiently carried out on the PP-RC1000 board using a high level language for hardware design, "Handel-C".A high sensitivity CMOS photoreceiver incorporating a high multiplication gain avalanche photodiode
http://dl-live.theiet.org/content/conferences/10.1049/cp_20040539
A photoreceiver consisting of a monolithically integrated avalanche photodiode and a CMOS transimpedance amplifier is presented. The sensitivity has been analysed theoretically through simulations and a detailed noise analysis. Sensitivity results are presented based on the OEIC being fabricated in a 1.5 μm CMOS process. At 2 Gb/s, the receiver has sensitivities of -33.5 dBm and -34.7 dBm for 650 nm and 850 nm light respectively, which exceed the performance of other reported CMOS photoreceivers.LLAMA: a Monte Carlo power estimation tool
http://dl-live.theiet.org/content/conferences/10.1049/cp_20040621
The design of low-power digital circuits has become a topic of great relevance in recent years, with increased consumer interest in portable, battery operated communications and computing. Aiming for low-power performance requires a robust methodology for the estimation of the likely power consumption of circuits and system in advance of their fabrication. The Monte Carlo parameter estimation technique is a general method that has found application in recent years as a useful approach to CMOS power estimation, particularly when used in conjunction with a simulation engine such as SPICE. Transistor-level circuits are particularly amenable to this technique. This paper describes an implementation of a first-order MC method, which is used to determine the average power estimation of CMOS digital circuits, based on netlists extracted from the circuit layout. Power estimates for a variety of circuits are presented.CMOS transimpedance amplifier for use with multiple APD geometries
http://dl-live.theiet.org/content/conferences/10.1049/cp_20040538
A transimpedance amplifier (TIA) capable of meeting the 500 MHz bandwidth requirement of IEEE1394 using avalanche photodiodes of any diameter from 20 μm to 250 μm is presented. A range of different sized photodiodes were simulated with the transimpedance amplifier using Agilent's ADS and the AustriaMicroSystems (AMS) 0.6 μm CMOS process. The feedback resistor of the TIA is varied to maintain a consistent 500 MHz bandwidth, independent of the detector size. The simulations predict a transimpedance gain of 354 Ω for 250 μm diameter detectors and 507 Ω for 20 μm diameter detectors at the 500 MHz bandwidth.Simulation of magnetic components in electric circuits using a coupled Spice-finite element analysis approach
http://dl-live.theiet.org/content/conferences/10.1049/ic_20020171
This paper shows how magnetic components modeled using the finite element method can be integrated into a Spice simulation of the circuit using a direct coupling approach. Previous methods have usually incorporated finite elements into a circuit simulation or vice versa, but this approach allows optimal modeling using each type of solver. Other methods of magnetic component characterisation using repetitive finite element analysis are also well documented, and while this is useful for simple topologies, the number of simulations required increases exponentially as the number of possible winding combinations also increases. It is envisaged therefore, that this method becomes relatively more applicable for more complex magnetic structures. The paper details the hybrid modeling approach and demonstrates the method using examples. (2 pages)Variable frequency to constant frequency converter (VFCFC) for aircraft applications
http://dl-live.theiet.org/content/conferences/10.1049/cp_20020120
The simulation of a 20 kW VFCF converter for aircraft applications has been investigated using the SABER simulation tool. The results are compared with the international standard and are very encouraging. Experimental results have shown the THD spec requirements for the input and output stages were met. Furthermore the system responds well under transient conditions. From the input waveform it can be seen that there are high frequency pulses injected back from the VFCFC to the supply. These could be readily removed by connecting a high frequency filter to the input side.A study of inverter operation in small induction motor drives
http://dl-live.theiet.org/content/conferences/10.1049/cp_20020142
Small (< 2 kW) variable speed induction motor drives increasingly find application in many domestic and light industrial applications such as small machine tools, pumps and domestic appliances where they can replace single-phase induction motors or universal motors. Their benefits are widely recognised, particularly improved performance and lower energy consumption. However, the cost and complexity of the inverter remain barriers to the wider adoption of brushless drives. Voltage source inverters using IGBTs are the industry standard for induction motor drives in this range. It is therefore important to study inverters to optimize their design to minimize losses. This reduces the thermal management required, which has a significant effect on the cost of the drive. The losses in an inverter depend on the choice of IGBT and diode, the switching frequency and modulation scheme. Circuits to limit the dV/dt and di/dt also affect the losses. It is therefore important to explore the IGBT's operation under real circuit conditions. The authors present a modelling exercise in PSpice to understand the effect of these factors on inverter losses as this understanding allows inverter designs can be optimized for low power losses without compromising reliability, cost and EMC standards. A model which accurately represents real circuit conditions and would enable the design to be optimized without building and testing numerous inverter prototypes.Low-power synthesis flow for regular processor design
http://dl-live.theiet.org/content/conferences/10.1049/ic_20010018
The paper presents the development of a low-power synthesis flow for the development of dedicated silicon circuits for data-dominated applications such as DSP systems. The work was carried out as part of a European ESPRIT low power action and a collaborative “low-power” project involving the universities of Liverpool Manchester and Sheffield. The design flow is briefly described and some results are presented for multiplier implementations and their use in the development of a discrete cosine transform (DCT) circuit. (5 pages)Designing low distortion continuously variable attenuators for microwave frequencies
http://dl-live.theiet.org/content/conferences/10.1049/ic_20010016
The paper briefly reviews commonly used attenuator topologies. The requirements of an FET I-V model for nonlinear simulation of attenuator circuits are stated. An improved MESFET/HEMT I-V model is then described. The properties of ac coupled stacked cold FET structures are briefly discussed. Measurements on two pi FET attenuators and a double hybrid FET attenuator are presented. (8 pages)Accurate power estimation technique with application to low-power recursive digital filter design
http://dl-live.theiet.org/content/conferences/10.1049/ic_20010012
In this work, we describe a new gate-level, pattern-based simulation tool (termed GCT) that uses a new technique in modeling the switching activities of digital circuits. By re-scaling the amplitude of each glitch transition, a better accuracy in estimating the power consumption is achieved with a minimal penalty in terms of the simulation run-time. The new technique is suitable for measuring power consumption of glitch-rich structures such as data path circuits. In this work the GCT is used to assist the development of low-power wave digital filters (WDFs). It will be seen that a reduction of power by up to 30-50% from conventional array designs without voltage scaling is achievable using pipelined WDF structures through a removal of glitches alone. (6 pages)A simulation study to quantify the advantages of silicon-on-insulator (SOI) technology for low power
http://dl-live.theiet.org/content/conferences/10.1049/ic_20010017
Combines the advantages of silicon-on-insulator (SOI) technology with asynchronous design techniques to assess the overall benefits in reducing power. A 16-bit self-timed adder is employed as the demonstrator circuit. At the technology level, fully-depleted SOI offers advantages compared with bulk CMOS. These arise due to lower subthreshold slope, lower vertical electric field hence enhanced channel mobility and reduced junction capacitance. The superior offstate current of SOI enables the threshold voltage to be lowered enhancing the current drive properties of SOI technology and enabling further power reduction without the loss of performance. At the architectural level of design, the adoption of asynchronous timing rather than a global clock reduces power. Here, the synchronous clock is replaced by local handshake signals between blocks. Although asynchronous control tends to be larger than in synchronous systems, significant power savings should result as the clock generation, drivers, and distribution are consuming around one third of the power in large, complex, high performance systems. (6 pages)Modeling the reality
http://dl-live.theiet.org/content/conferences/10.1049/ic_20000515
There is a strong need to model the future 'System on Chip' with a behavioral description. This is the best way to divide and conquer and is also the only way to measure the discrepancy between our human understanding and the rich complexity ofa real solution. A behavioral model implies a strong effort of simplification. The modeling represents a tough work but is necessary to make a good identification of the key parameters and a correct assessment of the design risks. We believe that an appropriate cycle-driven simulator with the right level of asynchronism is currently the best answer to the simulation of these systems. The presentation will describe in deeper details the characteristics of such an ideal simulator. We will see that the solution could imply to use a software so open that currently no software houses are willing to develop. (2 pages)Log-domain filter design with XFILTER
http://dl-live.theiet.org/content/conferences/10.1049/ic_20000488
Log-domain synthesis procedures for both ladder and cascade-biquad filters have been presented. The ladder design procedure is based on decomposing a matrix description of a prototype ladder and establishing an exponential relationship between the linear and nonlinear variables. This, in conjunction with the direct realisability of the matrix equations, facilitates the generation of various high-order log-domain designs from a single prototype. Design equations for second order and first order sections have also been presented for the design of cascade-biquad log-domain filters. The incorporation of these synthesis procedures in XFILTER represents an early attempt to automate the log-domain filter design process, which hitherto has mainly been performed manually. Due to the generality of the mapping process, the proposed design procedures can be readily extended to weak-inversion CMOS and other realisations which employ sinh and tanh companding functions. Various design examples have been given for validation. (7 pages)A 200 MHz CMOS analogue-ROM based direct digital frequency synthesiser
http://dl-live.theiet.org/content/conferences/10.1049/ic_20000480
A novel, low power frequency synthesiser system with 60 MHz output bandwidth is reported which is suitable for integration in a single chip RF transceiver. The system is based upon a conventional DDFS architecture. However, the problems which usually arise from the non-ideal behaviour in the DAC and the high power consumption of a ROM are avoided by using a non-volatile analogue memory array. Simulation results are presented which show that the system is suitable for use in an RF transceiver. (6 pages)PLLXPERT: an EDA tool for clock synthesis PLL generation
http://dl-live.theiet.org/content/conferences/10.1049/ic_20000516
On chip PLL's have become a standard integrated block for Systems on Chip (SoC), however, they still consume a disproportionate amount of design and layout resources. This paper describes an EDA tool, “PLLXpert” which simplifies and accelerates all tasks associated with the design and deployment of high performance clock synthesis PLLs. An important feature of the tool is that it is targeted at digital designers and does not require any understanding of PLL architectures. The user specifies the input and output clock relationships and the tool outputs all files required to instantiate the design in an SoC. (4 pages)Open source RISC processor for system on a chip applications
http://dl-live.theiet.org/content/conferences/10.1049/ic_20000524
This paper presents a simple RISC processor that allows the user to add customized instructions to accelerate key algorithms. The new instructions are added by modifying the HDL description of the processor. The processor can be programmed and the added instructions can be accessed through a high level language. The use of such features is demonstrated through examples of Reed Solomon decoding and the Log-MAP algorithm used in decoding Turbo codes. The examples show that considerable improvements in performance can be achieved by adding specific specialized instructions. Such features should be of use in future system on a chip applications that will require such algorithms to be implemented efficiently. (22 pages)The design of a 4.5 GHz CMOS tuned oscillator for clock and data recovery applications
http://dl-live.theiet.org/content/conferences/10.1049/ic_20000484
Describes the design of a 4.5-GHz CMOS tuned oscillator for clock and data recovery applications which has been implemented in a 0.18μm copper CMOS ASIC process. A basic comparison has also been made between harmonic and ring oscillator circuits and the potential advantages of the harmonic oscillator for use within high frequency PLL applications has also been covered. Improvements have also been suggested in both the design and simulation of these circuits to improve the performance of future designs. (12 pages)High-order log-domain filters: limitations and challenges
http://dl-live.theiet.org/content/conferences/10.1049/ic_20000489
Deals with the presentation of HSPICE simulation results corresponding to differential class-A fifth-order lowpass, sixth-order bandpass and tenth-order bandpass ladder log-domain filters. In every case the elliptic approximation was used. The filters were synthesised by virtue of an appropriately extended version of the XFILTER CAD package. Examples of the impact of the finite BJT current gain were provided. Moreover, simple circuit modifications leading to improved responses were reported. Measured results from several fabricated test-chips are given. (9 pages)42 V load dump transient and centralised active suppression
http://dl-live.theiet.org/content/conferences/10.1049/ic_20000449
The aim of this paper is to characterise the load dump characteristics of a three-phase, 42 V, 6 kW alternator using SPICE modelling techniques. The specification calls for a maximum overvoltage of 58 V. The purpose of the limited voltage is to improve safety and also enable the use of lower voltage semiconductors thereby reducing cost. In order to be able to use a centralised active clamp, the load dump period has to be kept short to reduce as much as possible the energy to be dissipated. This is achieved by the design of the field winding excitation circuit. (3 pages)Analogue high-level synthesis for mixed-signal IC realisation using an Analogue Design Synthesis Assistant (ADSA)
http://dl-live.theiet.org/content/conferences/10.1049/ic_20000479
The ADSA system is integrated within the CADENCE DFII framework and provides a user-guided environment to support high-level analogue synthesis. Synthesis is based upon multi-level optimisation and the user has flexibility in either using sensitivity-based or knowledge-based guidance of the optimisation process. A key feature is the accommodation of interaction between analogue blocks; this process is based upon successive refinement of behavioural models and the transfer of modelling data both up and down the design hierarchy. (7 pages)"How to design RF circuits" - oscillators
http://dl-live.theiet.org/content/conferences/10.1049/ic_20000146
Readily available harmonic balance simulators can be used to accurately predict the frequency, output power and harmonic content of RF and microwave oscillators. Phase noise can also be simulated, although values are highly dependent on the flicker noise parameters within the non-linear model. In the absence of a non-linear simulator, a relatively cheap small-signal simulator can still be used to predict frequency. Output power can be estimated by assuming 10-20% DC-to-RF efficiency. In reality, the small-signal simulation is vital to ensure that adequate negative resistance is available for start-up of oscillation. As a rule of thumb a negative resistance some 20% greater than the sum of the total positive resistances should be created. The small-signal simulation also illustrates the potential for unwanted or spurious frequencies of oscillation, at which the presence of negative resistance must be avoided. (7 pages)PSpice model for asymmetrical two-phase induction motors
http://dl-live.theiet.org/content/conferences/10.1049/cp_20000237
Simulation models for two-phase induction motors are often based on the reference frame theory and utilise mathematical programs to solve the differential equations and compute stator currents. In general these models lack the capability of incorporating nonlinear semiconductor behaviour for power electronic circuits. In this article a PSpice simulation model for an asymmetrical two-phase induction motor is proposed to model the motor with semiconductor based power converter circuits. A model validation is performed and simulation results are shown.SCALC: low-cost microwave network analysis and optimisation
http://dl-live.theiet.org/content/conferences/10.1049/ic_19990379
SCALC is low-cost analysis and optimisation package for linear (small-signal) RF networks. It makes extensive use of S-parameters, and thus SCALC is particularly suitable for applications in the VHF to microwave region. SCALC can analyse networks of up to 20 circuit elements, comprising passive components (with parasitic reactances and finite Q) and active components that are characterised by files of frequency-dependent S-parameter data. The results of an SCALC analysis are also S-parameters, which can be saved to similar datafiles, and can later be recalled into a higher-level system analysis. Unlike most low-cost analysis packages, SCALC includes a powerful optimiser. This paper will introduce the main features of SCALC and present some simple examples of its use. (5 pages)Experience of developing and using CAD tools for III-V FETs effectively in a nonideal world
http://dl-live.theiet.org/content/conferences/10.1049/ic_19990377
This paper describes the experience gained in developing and using CAD tools for the design of low distortion and nonlinear FET circuits using III-V technology. It includes a description of the CAD packages used, key features required in the CAD packages for realistic simulation, techniques for small and large signal “quick look” assessment for choosing bias and load and some example circuits where the tools have been used successfully. (16 pages)