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Please follow the links to view the publication.A 16nm SRAM design for low power and high read stability
http://dl-live.theiet.org/content/conferences/10.1049/ic.2011.0045
SRAM memory design in nanoscale regime has become increasingly challenging due to the reducing noise margins and increased sensitivity to threshold voltage variations. To overcome these challenges, different memory cells have been proposed for SRAMs with different transistor structures. These designs improve the cell stability in the subthreshold regime but suffer from bitline leakage noise, placing constraints on the number of cells shared by each bitline. In this paper, we propose a novel 11T SRAM cell topology which achieves cell stability as well as prevents bitline leakage. In addition to that, the proposed cell shows appreciable improvement in the dynamic power consumption. The HSPICE simulation and analysis at a 16nm feature size in CMOS process shows that the bitline leakage power consumption of the proposed 11T SRAM cell is reduced by 38% and the dynamic power consumption is reduced by 54% when compared to the existing 10T SRAM cell, while maintaining the read static noise margin nearly twice that of conventional 6T SRAM circuit.Intelligent power module with integrated SOI gate driver IC for medium power applications
http://dl-live.theiet.org/content/conferences/10.1049/ic_20080216
Intelligent power modules (IPM) with fully integrated solutions which combine both driving circuitry and power bridges on a single die or at least with implemented IC- based drivers replacing conventional hybrid IGBT and MOS drivers are restricted to low power applications (600 V, 1200 V, < 30 A). To develop the medium power market the extension of the current range of the IPMs from 30 A up to 100 A is necessary. A novel approach for medium power IPMs combining well established CIB (converter inverter brake) modules based on Semikron's Mini-SKiiP Technology with advanced silicon on insulator (SOI) gate driver ICs in a reliable cost effective package and with exccellent cooling is presented in this paper.Stable FDTD on disjoint domains - a discrete Green's function diakoptics approach
http://dl-live.theiet.org/content/conferences/10.1049/ic.2007.1344
We have developed stable radiative boundary conditions for FDTD on a union of arbitrary disjoint 2D domains. The associated self-consistent finite look-back scheme is constructed via the Z-domain with the aid of Schwarz' exterior formula. (6 pages)Impedance matching circuit design and optimisation for broadband power line communications
http://dl-live.theiet.org/content/conferences/10.1049/cp_20061895
This paper presents a numerical optimisation approach to an impedance matching circuit design for broadband power line communications. The proposed numerical optimisation method can be used to design any impedance matching circuit topology with the optimal circuit parameters for a broadband power line modem to match its power line connection point impedance measurements. The method has been tested based on filed measurements from one field substations of EdF in France. The enhancement of the gain performances is finally discussed. (5 pages)Systematic top-down design of a low-power continuous-time delta-sigma modulator wideband CDMA
http://dl-live.theiet.org/content/conferences/10.1049/cp_20050143
In this paper a systematic top-down design method for analog-to-digital converters is presented. Starting at a very high level, with only specifications for the DR, SNDR and bandwidth, the converter architecture is selected. This is followed by high level simulation. The results are then used in a building-block topology selection step, followed by an automatic sizing step and full transistor-level simulation. In this case a continuous-time delta-sigma modulator, suited for wideband CDMA, was designed. The circuit was manufactured in a 0.18 μm CMOS technology and reaches more than 60 dB SNDR in a bandwidth of 1.92 MHz.Digital architecture for background calibration of pipeline ADCs
http://dl-live.theiet.org/content/conferences/10.1049/cp_20050171
Continuous digital calibration technique suitable for implementation in a fully monolithic pipeline analog-to-digital converter (ADC) is presented here. The technique utilizes the existing digital calibration algorithm and extends it to work in real-time. This is accomplished by introducing two additional stages at the end of the pipeline which allow for a conversation cycle to be freed for calibration purposes. Two additional pipeline stages are active only during calibration process. Digital architecture discussed here is transparent to the overall system and is demonstrated using a 14-bit ADC, with 1-bit per stage topology and 18 identical stages (including two additional calibration stages). Proposed scheme successfully correct the dominant static errors present in a pipeline. Simulation results show more than 2-bits improvement in the number of effective bits and more than 20 dB improvement in the dynamic range of the converter.Analogue circuit synthesis from performance specifications
http://dl-live.theiet.org/content/conferences/10.1049/ic_19971119
Global optimisation techniques such as simulated annealing have been successfully applied to the digital synthesis problem. In this paper we describe how this technique has been applied to the synthesis of analogue circuits. To date, simulated annealing has been used to select component values, but the approach is being extended to topology selection. (6 pages)Automated generation of system-level AHDL architectures using a genetic algorithm
http://dl-live.theiet.org/content/conferences/10.1049/ic_19971120
This paper presents a methodology for the automated generation of optimised system-level AHDL architectures from AHDL system-level specifications using a GA. The synthesis process begins with a set of randomly generated system-level topologies and model parameters. Genetic operators, selection, crossover and mutation, are applied to evolve the population of topologies to a population of system-level architectures in which topologies and model parameters meet the required performance specifications. Both topology and model parameters evolve simultaneously. Simulations are performed in the time domain with an AHDL behavioural model library of system-level building blocks. The integration and exploitation of AHDL simulation based design allows for an efficient and flexible system-level synthesis methodology with less dependency on a knowledge-based approach and complex design equations. The methodology has been successfully demonstrated for the design of a DSB-SC-AM demodulation chain, for which an optimised system-level AHDL architecture has been produced fulfilling the required input AHDL system-level specification. (7 pages)Interleaved switching topology for three-phase power-factor correction
http://dl-live.theiet.org/content/conferences/10.1049/cp_19940978
Single-switch boost stages, connected between three-phase rectifiers and DC link capacitors, allow good power factor correction when operated in the discontinuous conduction mode. This paper is presented to aid design at all operating levels of this power converter type. For high output power, it is shown that reduced component stress and higher power factor results from the use of interleaved switching topologies. Some experimental results from a laboratory model are presented.Diode–capacitor voltage multipliers combined with boost-converters: topologies and characteristics
http://dl-live.theiet.org/content/journals/10.1049/iet-pel.2011.0215
Various topological modifications of diode–capacitor voltage multipliers are considered. All the topologies are based on two known schemes: Cockcroft–Walton and Dickson. These topologies are built combined with a boost-converter, operating at a high switching frequency. Such a solution allows reducing the values of the capacitors. The proposed topologies can also be used by feeding them directly from a three-phase network through the regular rectifier; in this case the influence of such circuits on a supply network is reduced. A number of novel modifications of multipliers, having their specific features, are obtained. The procedure of calculating the output voltage, depending on the capacitor values and load parameters is proposed and the design formulas for the output voltage of some of the schemes are developed. It is shown that a decrease in the output voltage is caused by some sort of internal resistance. The essentially similar operating modes of different topologies are characterised by a different value of such a resistance, and accordingly by a different internal voltage drop. Dynamic models for some of the proposed topologies are also developed. The computer simulation and the experimental results proved the theoretical expectations.Compact X-band SiGe power amplifier for single-chip phased array radar applications
http://dl-live.theiet.org/content/journals/10.1049/iet-map.2012.0014
An X-band power amplifier (PA) is presented for single-chip phased array radar applications. In this work, the choice of optimum circuit topology for X-band PA design is discussed and possible stability issues for high and low frequencies are analysed. The PA features a two-stage cascode architecture that includes both high-speed (low breakdown) and high breakdown (low-speed) SiGe transistors. It consists of two stages providing a 23.2 dBm saturated output power with a 28% power-added efficiency at 9 GHz. The output 1-dB compression point (<i xmlns="http://pub2web.metastore.ingenta.com/ns/">P</i><sub xmlns="http://pub2web.metastore.ingenta.com/ns/">1dB</sub>) is higher than 20 dBm in a 3 GHz bandwidth and has a maximum value of 22.2 dBm. The small-signal gain is 25.5 dB with a 3-dB bandwidth of 3.2 GHz (7.3–10.5 GHz). The PA has been fabricated using 0.25 µm SiGe BiCMOS process provided by IHP Microelectronics. The PA occupies 1 mm×0.6 mm chip area and consumes 120 mA from a 4 V supply voltage. These results demonstrate comparable or better performance than other reported PAs and suitable performance for single-chip phased array applications.Innovative power distributed amplifier using the Wilkinson combiner
http://dl-live.theiet.org/content/journals/10.1049/ip-map_19951770
A topology of a power-distributed amplifier, improved by the insertion of an input Wilkinson divider and an output Wilkinson combiner, is presented. The advantages of the new configuration, in small signal and power performance, are demonstrated by comparison with a conventional configuration, for wide-band power applications. The opportunity to use more than two FETs makes the new configuration attractive and enables one to overcome the limitations of the typical binary power configurations.Unity power factor rectifier–inverter structure operating under unbalanced supply and variable DC bus voltage
http://dl-live.theiet.org/content/journals/10.1049/iet-pel.2010.0139
A recently introduced method of improving converter input current waveforms as well as power factor are re-evaluated under non-ideal operating conditions, that is, variable DC bus and unbalanced supply. The proposed method makes use of a novel controlled front-end diode rectifier of a rectifier–inverter structure. The technique involves the use of bi-directional bi-pass switches across the front-end rectifier, with a dSPACE-based intelligent control algorithm. The operation of the converter is fully analysed as possible DC/AC drives and a complete design example is provided. The main feature of the topology is low cost, small size, high power factor and simplicity. It is found to be a universal retrofit for DC drives, and in the front-end rectifier of existing three-phase AC drives, UPS etc. for power factor correction without any passive or active filtering.High/low-impedance transmission-line and coupled-line filter networks for differential phase shifters
http://dl-live.theiet.org/content/journals/10.1049/iet-map.2010.0245
Two compact and simple to design differential phase shifter topologies, based on high/low-impedance transmission-line sections and open-ended coupled-line sections, are presented for the first time. The basic circuit theory for single section topologies is reviewed, leading to design equations and graphs for direct circuit synthesis. Balanced topologies and multiple section designs are also proposed improving the performance and feasibility of the phase shifters. Two planar microstrip single section differential phase shifter hybrids, at a centre frequency of 12 GHz and a 45 and 135° phase difference have been designed and manufactured. The designs have a simulated 0.5 dB amplitude and 1° phase imbalance over more than 25 and 40% bandwidth, respectively. Experimental results verify the circuit performance and feasibility of the proposed differential phase shifters.Load pull methodology to characterise class-E outphasing power amplifiers
http://dl-live.theiet.org/content/journals/10.1049/iet-map.2011.0371
A novel load pull methodology to characterise the performance of class-E outphasing power amplifiers is presented. The traditional analysis of the outphasing topology cannot be applied when class-E amplifiers are used because these amplifiers do not behave as an ideal current or voltage source. Unlike most other amplifier classes, class-E amplifiers require a phase-modulated input signal with constant amplitude. Additionally, class-E amplifiers have non-linear transfer characteristics which are a function of the load impedance. The methodology presented here is based on finding the load locus in the load pull plane of an individual class-E amplifier. Then the performance of the two class-E amplifiers in the outphasing topology is readily obtained. The key advantage of the method is that the load pull characterisation of only a single amplifier is required. The methodology is general in that any passive load combining circuit can be used and any amplifier combination can be used in the outphasing topology provided that their load pull data are available. The load locus is derived without any reference to the phase difference between the drive signals.1-port topology of the degree-1 and 2 terminated circulator
http://dl-live.theiet.org/content/journals/10.1049/ip-map_20000812
The equivalent circuit in the impedance plane at port-1 of a 3-port circulator with ports 2 and 3 terminated in ideal resistive loads is a classic result. The purpose of the paper is to synthesise 1-port topology in the admittance plane in the case for which ports 2 and 3 are terminated in real resistive loads and in that for which the ports are loaded by broadband matching networks. This is done in terms of the eigenvalues of the problem region under the assumption that the in-phase eigen-network may be idealised by a short-circuited boundary condition and an ideal 2-port gyrator circuit. The real part circuit and those at the split frequencies of the counter-rotating eigenvalues are also deduced as a preamble to realising the general circuit. The properties displayed by these circuits are compatible with existing experimental procedures for this class of device.Direct synthesis of transmission line low-/high-pass filters with series stubs
http://dl-live.theiet.org/content/journals/10.1049/iet-map.2008.0259
A direct synthesis procedure is presented for the design of transmission line low-/high-pass filters with series stubs. The proposed prototype consists of a cascade of series stubs of electrical length thetas<sub xmlns="http://pub2web.metastore.ingenta.com/ns/"><i>c</i></sub> alternating with uniform transmission lines of electrical length 2thetas<sub xmlns="http://pub2web.metastore.ingenta.com/ns/"><i>c</i></sub>. An exact network synthesis technique is applied on the fully frequency-distributed transmission line filter structures. By short-circuiting these series stubs, a low-pass prototype can be established to synthesise the filters with both predictable in-band and out-of-band behaviours. Instead, if the series stubs are open-circuited, a quasi-high-pass or wide band-pass filter can be designed with specified frequency bandwidth and centre frequency. Based on the formulation of a transfer function, a set of closed-form design formula is derived so that the synthesis design can be carried out for the proposed filters with Chebyshev equal-ripple frequency responses in the concerned low- and high-pass bands. As design examples, two five-pole planar filters based on the low- and high-pass topologies are implemented by using hybrid slotline and coplanar-waveguide structures. After final optimisation is executed via full-wave electromagnetic software to take all the discontinuities into accounts, two designed filters are fabricated and measured to verify the proposed synthesis approach and confirm the theoretical predictions.TLM diakoptics for coupled-mode analysis of GaAs MESFET distributed amplifier
http://dl-live.theiet.org/content/journals/10.1049/ip-map_19960427
A new model of the application of diakoptics in the transmission-line-matrix (TLM) method for the coupled-mode analysis of GaAs MESFET distributed amplifiers is proposed. The model takes into account the major coupling effect caused by <i xmlns="http://pub2web.metastore.ingenta.com/ns/">C<sub>dg</sub></i> and <i xmlns="http://pub2web.metastore.ingenta.com/ns/">g<sub>m</sub></i> of the active devices. Techniques are developed by representing the whole system as two coupled lossy transmission lines. The numerical effort required can be reduced by representing the response of the resultant coupled system as that of a superposition of two independent modes. The scattering matrix of the system obtained in the time domain leads to a process of discrete time domain convolutions based on the TLM numerical procedure. The results are compared with other analytical and computed results and show good agreement.Recursive algorithm for noise analysis of a two-port network with arbitrary internal topology using the S-wave approach
http://dl-live.theiet.org/content/journals/10.1049/ip-map_19941329
Using the wave representation, a recursive algorithm for noise analysis of a two-port network with an arbitrary internal topology is presented. In contrast with past analyses, the evaluation of the 2N*2N matrix inversion is avoided, which results in less computer storage and reduced computation time. The approach unifies Gupta's (1981) multiconnection method for signal analysis with the noise analysis. To demonstrate the accuracy of this method, the noise of a 1-7 GHz 10 dB distributed amplifier is calculated. The results obtained are in excellent agreement with the simulated results using the HP Microwave Design Software (MDS).Voltage-driven class E amplifier and applications
http://dl-live.theiet.org/content/journals/10.1049/ip-map_20045159
A voltage-driven class E power amplifier topology is presented. The operating principle of the circuit is explained, and measurement results for a MIC implementation using an OMMIC ED02AH 6×50 μm pHEMT as the active device are given. At the nominal operating frequency of 870 MHz, the MIC achieves 18 dB maximum gain, produces 18 dBm output power, and a maximum power added efficiency of 93%.Analysis and design of high-efficiency variable conduction angle Doherty amplifier
http://dl-live.theiet.org/content/journals/10.1049/iet-map.2007.0307
The Doherty amplifier was first proposed to improve the efficiency under output power back-off using the technique of load-line modulation of a ‘carrier’ amplifier through a ‘peak’ amplifier. By varying input bias of the peak amplifier along with load of the carrier amplifier at low drive levels, different topologies of the Doherty amplifier are distinguished. An analytical analysis that determines the optimum output performance of these topologies in terms of output power, efficiency and output power back-off ensuring a near-peak efficiency is developed. The presented comprehensive analysis considered for variation of conduction angle of the peak amplifier biased class C. New design equations of the analysed topologies are derived. A realisation at a central frequency of 1.9 GHz using GaAs field effect transistor (FET) devices of a Doherty amplifier topology is reported. In this topology the carrier operates (at low drive levels) into load impedance 5/2 times larger than its optimum. Power-added efficiency of 61.8% is measured at <i xmlns="http://pub2web.metastore.ingenta.com/ns/">P</i><sub xmlns="http://pub2web.metastore.ingenta.com/ns/">1 dB</sub> of 25.9 dB m and 33.2% is measured at 9 dB back-off from <i xmlns="http://pub2web.metastore.ingenta.com/ns/">P</i><sub xmlns="http://pub2web.metastore.ingenta.com/ns/">1 dB</sub>.Symbolic analysis of large-scale microwave networks
http://dl-live.theiet.org/content/journals/10.1049/ip-map_19941309
A new and efficient method of symbolic analysis of the interconnection of microwave networks which are characterised by the wave-scatter matrices is presented. By taking advantage of unique topological properties of the networks, a rather simplified SFG (referred to as compact SFG (signal flow graph)) is introduced with which the effective symbolic products combination can be determined with great simplicity and clarity so that large-scale microwave networks can be treated. An augmented network principle is also derived so that all the elements of the wave-scatter matrix of the connected network can be obtained in one implementation.Approach to determine voltage control areas considering impact of contingencies
http://dl-live.theiet.org/content/journals/10.1049/ip-gtd_20041134
This paper presents an efficient method for the formation of voltage control areas. The proposed method considers the effect of <i xmlns="http://pub2web.metastore.ingenta.com/ns/">P</i>–<i xmlns="http://pub2web.metastore.ingenta.com/ns/">V</i> and <i xmlns="http://pub2web.metastore.ingenta.com/ns/">Q</i>–<i xmlns="http://pub2web.metastore.ingenta.com/ns/">δ</i> coupling and changes in network topology. The full Newton Raphson load flow (NRLF) Jacobian sensitivities and voltage variations under contingencies have been used for the formation of the voltage control areas. These areas have been reduced to equivalent nodes using the REI reduction technique, and the reduced network has been validated for the voltage stability analysis. The effectiveness of the method has been established on the IEEE 14-bus system and a practical 75-bus Indian system.Variable gain amplifier circuit using titanium dioxide memristors
http://dl-live.theiet.org/content/journals/10.1049/iet-cds.2010.0210
A variable gain amplifier (VGA) topology utilising titanium dioxide (TiO<sub xmlns="http://pub2web.metastore.ingenta.com/ns/">2</sub>) memristors is presented. The circuit is analysed based on recently published charge-controlled and voltage-controlled memristor models. The analysis includes a theoretical prediction of total harmonic distortion for the amplifier as a figure of merit. The theoretical results are supported with SPICE circuit simulation including a memristor macromodel.Efficient implementation of distributed routing algorithms for NoCs
http://dl-live.theiet.org/content/journals/10.1049/iet-cdt.2008.0092
Chip multiprocessors (CMPs) are gaining momentum in the high-performance computing domain. Networks-on-chip (NoCs) are key components of CMP architectures, in that they have to deal with the communication scalability challenge while meeting tight power, area and latency constraints. 2D mesh topologies are usually preferred by designers of general purpose NoCs. However, manufacturing faults may break their regularity. Moreover, resource management frameworks may require the segmentation of the network into irregular regions. Under these conditions, efficient routing becomes a challenge. Although the use of routing tables at switches is flexible, it does not scale in terms of latency and area due to its memory requirements. Logic-based distributed routing (LBDR) is proposed as a new routing method that removes the need for routing tables at all. LBDR enables the implementation of many routing algorithms on most of the practical topologies we may find in the near future in a multi-core system. From an initial topology and routing algorithm, a set of three bits per switch/output port is computed. Evaluation results show that, by using a small logic, LBDR mimics the performance of routing algorithms when implemented with routing tables, both in regular and irregular topologies. LBDR implementation in a real NoC switch is also explored, proving its smooth integration in the architecture and its negligible hardware and performance overhead.Delay approximation for synchronous filter topologies
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_20010288
It is shown that the original definition of <i xmlns="http://pub2web.metastore.ingenta.com/ns/">e</i> developed by Euler can be used as the basis of a delay approximation where all the poles have the same value. Furthermore, it is demonstrated that by splitting the Euler function into complex pole pairs, by the addition of an artificial variable β, an additional degree of freedom can be introduced. Through optimisation of the value of β it is shown that either the group delay or step response can be optimised. This delay approximation, when compared to a standard Bessel approximation, is shown to provide acceptable performance for many applications. Furthermore, it offers the considerable practical benefit of being realisable as a cascade of identical building block elements when appropriate technologies (e.g. second-order active filter blocks) are used.Graph-based detailed router for hierarchical field-programmable gate arrays
http://dl-live.theiet.org/content/journals/10.1049/ip-cdt_19990248
The paper presents a detailed routing algorithm for the hierarchical field-programmable gate arrays (HFPGAs). This algorithm is performed in two phases. First a multilevel HFPGA is transformed into a single-level HFPGA to find the initial routing results. The initial routing problem is reduced to the graph colouring and Steiner-tree problems. Two types of routing structure, disjointed and overlapped structures, are employed to specify different routing resources in order to improve the routing efficiency. In the second phase, the initial routing results are expanded to a multilevel HFPGA. Experimental results on a set of MCNC benchmark circuits show that the algorithm is very efficient. These results not only validate the claim on the performance of the algorithm but also facilitate the usage of the HFPGAs.Design of non-balanced cross-coupled oscillators with no matching requirements
http://dl-live.theiet.org/content/journals/10.1049/iet-cds.2010.0030
Using two-port network transmission parameters we derive the general characteristic equation of a cross-coupled circuit topology which involves two active devices and four or six impedances. The derived equations are generic and apply both to BJT or MOS transistors and even any other active device without any matching constraints. Application to realising novel non-balanced non-matched cross-coupled oscillators is demonstrated. Spice simulations of a MOS oscillator in a 0.25 µ technology are given as well as experimental results from an oscillator employing discrete Bipolar transistors.Transformer matrix of some transmission lines topologies
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19951390
A transmission line based transformer (TLBT) is described. It is shown that some topologies of transmission line elements imply transformer-like behaviour of the total arrangement. The expected application of the TLBT is in systems in which matching is required, for high frequency waveforms or for narrow pulse applications.Dual-mode design of fully differential circuits using fully balanced operational amplifiers
http://dl-live.theiet.org/content/journals/10.1049/iet-cds_20070280
Fully differential (F-D) analogue circuits are usually designed focusing only on their differential-mode (DM) behaviour, without considering common-mode (CM) responses. A technique is presented for the design of both DM and CM circuit responses, using fully balanced operational amplifiers (FBOAs) as analogue building blocks. FBOAs work with CM and DM voltages as a whole, having an ideally infinite gain for both modes. This allows independent design of CM and DM dynamics. Inverting and non-inverting F-D topologies can be implemented in a simple way, similar to the implementation of their single-ended counterparts. Some typical application circuits are analysed and discussed and, as a design example, a ‘double-mode oscillator’ (a circuit that has independent CM and DM oscillations) was built and experimentally evaluated.Approach to the synthesis of canonic RC-active oscillators using CCII
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19941398
A systematic approach has been employed to synthesise sinusoidal RC-active oscillators using second-generation current conveyor (CCII). The resulting topologies are canonic, i.e. they require the minimum number of active (a single CCII) and passive components (two capacitors and either two or three resistors) for realisation of both single-frequency oscillators (SFOs) and variable-frequency oscillators (VFOs). Oscillation condition (OC) and/or oscillation frequency (OF) can be adjusted using single resistors. It is shown that using a CCII as the active device provides RC oscillators with a minimum passive network (N<sub xmlns="http://pub2web.metastore.ingenta.com/ns/">GC</sub>). The configurations obtained have been classified in four groups in accordance to their coupling level between the OC and FO equations. Stability has been studied. All the oscillators have been tested and experimental results show very close agreement with the theoretical analysis.Customisation of on-chip network interconnects and experiments in field-programmable gate arrays
http://dl-live.theiet.org/content/journals/10.1049/iet-cdt.2010.0105
Conventional rigid and generalpurpose on-chip networks occupy significant logic and wire resources in field-programmable gate arrays (FPGAs). To reduce the area cost, the authors present a topology customisation technique, using which on-demand network interconnects are systematically established in reconfigurable hardware. First, the authors present a design of a customised crossbar switch, where physical topologies are identical to logical topologies for a given application. A multiprocessor system combined with the presented custom crossbar has been designed with the ESPAM design environment and prototyped in the FPGA device. Experiments with practical applications show that the custom crossbar occupies significantly less area, maintains higher performance and reduces the power consumption, when compared with the general-purpose crossbars. In addition, the authors present that configuration performance and cost can be improved by reducing the functional area cost in FPGAs. Second, a customisation technique for the circuit-switched network-on-chip (NoC) is presented, where only necessary half-duplex interconnects are established for a given application mapping. The presented customised NoC is implemented in FPGA and results indicate that the area is reduced by 66%, when compared with the general-purpose networks.CHiRPS: a general-area parallel multilayer routing system
http://dl-live.theiet.org/content/journals/10.1049/ip-cdt_19951619
A new, highly parallel model for concurrent multilayer routing, called CHiRPS (Configurable Highly Routable Parallel System), is presented. The nucleus of CHiRPS is a very flexible pathfinder that can be easily configured, even in the presence of obstacles, to generate various commonly used pattern-based routes, such as Steiner trees with single trunk, comb trees, contour-based routes, etc., that span multiple layers simultaneously. The authors employ the concept of a total grid-graph to capture the state of the routing region. The main steps of the pathfinder are based on new parallel algorithms for cycle detection, cycle elimination and tree reduction. The proposed algorithms scale well with increased problem sizes since they require only O(log N) time when given a grid-graph with up to N<sup xmlns="http://pub2web.metastore.ingenta.com/ns/">2</sup> nodes. As such, they are good candidates for massively data-parallel machines.Finding all DC solutions of nonlinear resistive circuits by exploring both polyhedral and rectangular circuits
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19970900
A new fast method for finding all the DC solutions of piecewise-linear (PWL) resistive circuits is presented. The structure of the algorithm is based on the exploration of a binary tree: each node represents a specific PWLsub circuit, derived from the original PWL circuit by truncating the original PWL characteristics. The terminal nodes of the tree represent the linear circuits related to single linear regions. The natural exponential growth of the tree is controlled by two different criteria. They are based on the investigation of the convex solution domains of the so-called polyhedral circuits or, alternatively, of the so-called rectangular circuits. The first criterion is more efficient but more CPU-time consuming than the second one. An appropriate combination of both allows the realisation of an overall algorithm faster than those based on a unique criterion.High input impedance VM-APSs with grounded passive elements
http://dl-live.theiet.org/content/journals/10.1049/iet-cds_20060196
Three new circuit topologies for first-order all-pass filters, each with two variations, realising six new first-order voltage-mode all-pass sections are proposed. Each circuit employs two differential voltage current conveyors and three grounded passive components, ideal for IC implementation. All the circuits possess high input impedance, which is a desirable feature for voltage-mode circuits. As an application, a new quadrature oscillator circuit is realised using one of the proposed all-pass circuits. PSPICE simulations using 0.5 µm CMOS parameters confirm the validity and practical utility of the proposed circuits.Smoothing of the nonlinearity of some algebraic characteristics by means of 1-port structures composed of similar elements
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_20050004
For a 1-port composed of similar passive ‘algebraic’ elements characterised by the monotonic polynomial characteristic <i xmlns="http://pub2web.metastore.ingenta.com/ns/">f</i>(·) (in the conductivity formulation, <i xmlns="http://pub2web.metastore.ingenta.com/ns/">i</i>=<i xmlns="http://pub2web.metastore.ingenta.com/ns/">f</i>(<i xmlns="http://pub2web.metastore.ingenta.com/ns/">v</i>)), the map <i xmlns="http://pub2web.metastore.ingenta.com/ns/">f</i>(·)→<i xmlns="http://pub2web.metastore.ingenta.com/ns/">F</i>(·), where <i xmlns="http://pub2web.metastore.ingenta.com/ns/">F</i>(·) is the input (port) characteristic (<i xmlns="http://pub2web.metastore.ingenta.com/ns/">i</i><sub xmlns="http://pub2web.metastore.ingenta.com/ns/"><i>input</i></sub>=<i xmlns="http://pub2web.metastore.ingenta.com/ns/">F</i>(<i xmlns="http://pub2web.metastore.ingenta.com/ns/">v</i><sub xmlns="http://pub2web.metastore.ingenta.com/ns/"><i>input</i></sub>)) of the 1-port is considered. The purpose is to compare the relative nonlinearity (curliness) of <i xmlns="http://pub2web.metastore.ingenta.com/ns/">F</i>(·) with that of <i xmlns="http://pub2web.metastore.ingenta.com/ns/">f</i>(·). It is shown that for the polynomial characteristics, the relative nonlinearity of <i xmlns="http://pub2web.metastore.ingenta.com/ns/">F</i>(·) is weaker than that of <i xmlns="http://pub2web.metastore.ingenta.com/ns/">f</i>(·). This result is useful for understanding basic nonlinear circuits, in particular grid-type circuits.Wave realisation of filters and equalisers in log-domain
http://dl-live.theiet.org/content/journals/10.1049/iet-cds_20070045
Log-domain circuits offer a low-power property, whereas wave-derived circuits inherit a low-sensitivity property from the ladder prototypes and are less prone to transistor non-idealities. A novel approach to the design of wave filters in the log-domain is presented and several wave two-port topologies are investigated. Important design properties are examined. Realisations of direct filters, complex filters and group-delay equalisers in typical BJT and HBT SiGe BiCMOS technologies are assessed. The design procedures have been incorporated into XFILTER design software.Low-power algorithm for automatic topology generation for application-specific networks on chips
http://dl-live.theiet.org/content/journals/10.1049/iet-cdt_20070049
As the number of cores on a chip increases, power consumed by the communication structures takes a significant portion of the overall power budget. Many application-specific systems on chips (SoCs) involve heterogeneous cores with varied functionality and communication requirements, such as those in mobile-phone systems. If a regular network-on-chip is designed to fit the requirements of few high-communicative components, it will be largely over-designed with respect to the needs of the remaining components. Consequently, irregular network architectures might be necessary for realising application-specific SoCs. The authors propose a power-aware topology construction method, which can construct application-specific low-power interconnection topologies according to the traffic characteristics of SoCs. They take several multimedia applications as case studies and experimental results show the power savings of power-aware topology approximate to 49% of the interconnection architecture. They also implement a simulator to experiment more general large scale systems, and the results show that customised irregular networks are clearly superior to traditional regular architectures in terms of performance and energy.Step-response optimisation techniques for low-power, high-load, three-stage operational amplifiers driving large capacitive loads
http://dl-live.theiet.org/content/journals/10.1049/iet-cds.2009.0126
Two simple efficient techniques to optimise the closed-loop transient response of three-stage amplifiers for large capacitive load applications are proposed and developed. The proposed approaches exploit a current comparator in the inner amplifier nodes to sense the input voltage transients and to switch on an auxiliary driving device providing slew-rate enhancement and settling time improvement without extra static power dissipation. SPECTRE simulations are carried out on a three-stage amplifier adopting a recently proposed reversed-nested Miller compensation strategy with a voltage follower and two nulling resistors, for which a novel design methodology is provided as well. Simulation results confirm the effectiveness of the two proposed techniques, showing a symmetrical step response with a significant improvement in large-signal speed performance. Both proposed solutions are suitable for any particular three-stage amplifier topology and are also independent of the adopted compensation network.Universal switch blocks for three-dimensional FPGA design
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_20040228
The authors consider the switch-block design problem for three-dimensional FPGAs. A three-dimensional switch block M with <i xmlns="http://pub2web.metastore.ingenta.com/ns/">W</i> terminals on each face is said to be universal if every set of nets satisfying the dimension constraint (i.e. the number of nets on each face of M is at most <i xmlns="http://pub2web.metastore.ingenta.com/ns/">W</i>) is simultaneously routable through M. A class of universal switch blocks for three-dimensional FPGAs is presented. Each of the switch blocks has 15<i xmlns="http://pub2web.metastore.ingenta.com/ns/">W</i> switches and switch-block flexibility 5 (i.e. <i xmlns="http://pub2web.metastore.ingenta.com/ns/">F</i><sub xmlns="http://pub2web.metastore.ingenta.com/ns/"><i>S</i></sub>=5). It is proved that no switch block with less than 15<i xmlns="http://pub2web.metastore.ingenta.com/ns/">W</i> switches can be universal. The proposed switch blocks are compared with others of the topology associated with those used in the Xilinx XC4000 FPGAs. Experimental results demonstrate that the proposed universal switch blocks improve routabilty at the chip level. Further, the decomposition property of a universal switch block provides a key insight into its layout implementation with a smaller silicon area.Efficient partitioning-based method to determine the upper bound on the number of operating points in transistor circuits
http://dl-live.theiet.org/content/journals/10.1049/ip-cds_19941245
An efficient method to assess the upper bound on the number of DC solutions is presented. It decomposes the original circuit into successive subcircuits by implementing a partitioning procedure, which is based on a topological analysis of the circuit. In a further step the uniqueness of the DC operating point is determined, and how many operating points can occur. Because the obtained subcircuits contain fewer nonlinearities, this process can be carried out in an efficient manner, resulting in a significant saving in the number of calculations. In addition, the circuit is described by a linear transformation of the well known MNA representation. This allows the method to be easily implemented in a simulation environment.50 GHz static frequency divider in 130 nm CMOS
http://dl-live.theiet.org/content/journals/10.1049/el_20083638
A novel circuit topology and design procedure to increase the operating frequency of current model logic (CML) static frequency dividers is proposed. The topology and design procedure are used to design a 50 GHz CML static frequency divider in 130 nm CMOS. The designed divider has a 20 GHz division bandwidth and consumes 11.7 mW power from a 1.5 V supply.Soft-switching converter based on bi-flyback topology
http://dl-live.theiet.org/content/journals/10.1049/el_20080849
A soft switching bi-flyback converter is presented. Two identical flyback converters are used in the proposed circuit to share the load current. Thus, the transformer copper losses and the conduction losses on the output diodes are reduced. An active snubber is adopted to reduce the voltage spike and realise the ZVS turn-on of switches at the transition interval. Thus, the switching losses and thermal stresses of the semiconductors are reduced. Experiments are provided to verify the effectiveness of the proposed converter.Dual-mode VCO gain topology for reducing in-band noise and reference spur of PLL in 65 nm CMOS
http://dl-live.theiet.org/content/journals/10.1049/el.2010.3553
A new topology in PLL architecture dual-mode <i xmlns="http://pub2web.metastore.ingenta.com/ns/">K</i><sub xmlns="http://pub2web.metastore.ingenta.com/ns/"><i>VCO</i></sub> (DMK) to reduce in-band noise and reference spurs is presented. The DMK PLL also adopts the technique to shrink the spurs by modulating the control voltage. The prototype DMK PLL is implemented in a 65 nm CMOS and shows about 3 ps RMS jitter, phase noise of −107 and −109 dBc/Hz at 100 kHz, 1 MHz offset frequency and reference spur of 68.5 dBc.Linearity improvement in biquadratic transconductor-C filters
http://dl-live.theiet.org/content/journals/10.1049/el_20072537
A new technique for improving the linearity performance in biquadratic transconductor-C filters is presented. This improvement has been achieved by applying some modifications to the filter topology which considerably relax the linearity requirement on transconductor circuits. Using very simple transconductors, 30 dB improvement in total harmonic distortion compared to the conventional approach has been observed.Current-feedback source-degenerated CMOS transconductor with very high linearity
http://dl-live.theiet.org/content/journals/10.1049/el_20030050
A highly linear current-feedback (CF) transconductor with resistive source-degeneration is developed in CMOS technology. It consists of a differential source follower cascaded with a classical source-degenerated transconductor with its drain current fed back to modulate the bias of the source follower for nonlinearity cancellation, yielding an overall linear transfer function in the circuit. Designed using a 0.35 µm CMOS process for a continuous-time delta-sigma application, the CF transconductor achieves the total harmonic distortion better than −80 dB up to 1 MHz for a 0.8 V input differential voltage while the supply voltage is 2.5 V and the power consumption is 3.4 mW.Low-voltage CMOS adjustable current mirror
http://dl-live.theiet.org/content/journals/10.1049/el.2010.3089
A novel scheme for an adjustable low-voltage CMOS current mirror is introduced. The proposed current mirror provides continuous gain adjustment, while it simultaneously features the attractive characteristic of low-voltage operation. The behaviour of the proposed topology has been experimentally verified through a first-order lowpass filter fabricated in AMS 0.35 µm CMOS technology.Wideband CMOS transimpedance amplifier
http://dl-live.theiet.org/content/journals/10.1049/el_20030398
A fully differential wideband CMOS transimpedance amplifier is presented. Simulation results of different inductive peaking configurations are shown. Measured performances give a 19 GHz bandwidth and 45 dBΩ transimpedance gain at 6.5 mW power consumption.Very fast carry energy efficient computation based on mixed dynamic/transmission-gate full adders
http://dl-live.theiet.org/content/journals/10.1049/el_20070752
A circuit approach based on the adoption of mixed dynamic and transmission-gate full adder topologies to achieve very fast computation in carry chains is discussed. From a design point of view, the approach is very simple and allows the design to exceed the speed performance of fast Domino logic by more than 30% without degrading the energy efficiency. Post-layout simulations on a 90 nm CMOS technology are presented to validate the results.Frequency-bandwidth-tunable powerline notch filter for biopotential acquisition systems
http://dl-live.theiet.org/content/journals/10.1049/el_20093704
Presented is a novel powerline notch filter embeddable into a chopper-stabilised instrumentation amplifier for biopotential measurements. The frequency-translation property of the chopper enables the powerline notching to be indirectly implemented by two resonant zeros around the chopper frequency, resulting in substantial silicon area savings. Transistor-level implementation in 90 nm CMOS using a pseudo-<i xmlns="http://pub2web.metastore.ingenta.com/ns/">LC</i> circuit topology with <i xmlns="http://pub2web.metastore.ingenta.com/ns/">Q</i>-enhancement demonstrates 50 to 60 Hz frequency tunability, 25/41 dB powerline rejection at 5/30 Hz bandwidth, and 1000× relaxation of time constant under a 4 kHz chopper frequency.