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The categorisation of network packets according to multiple parameters such as sender and receiver addresses is called packet classification. Packet classification lies at the core of Software-Defined Networking (SDN)-based network applications. Due to the increasing speed of network traffic, there is an urgent need for packet classification at higher speeds. Although it is possible to accelerate packet classification algorithms through hardware implementation, this solution imposes high costs and offers limited development capacity. On the other hand, current software methods to solve this problem are relatively slow. A practical solution to this problem is to parallelise packet classification using multi-core processors. In this study, the Thread, parallel patterns library (PPL), open multi-processing (OpenMP), and threading building blocks (TBB) libraries are examined and implemented to parallelise three packet classification algorithms, i.e. tuple space search, tuple pruning search, and hierarchical tree. According to the results, the type of algorithm and rulesets may influence the performance of parallelisation libraries. In general, the TBB-based method shows the best performance among parallelisation libraries due to using a theft mechanism and can accelerate the classification process up to 8.3 times on a system with a quad-core processor.
The increasing demand for high-performance computing has emphasised the invocation of sophisticated multi/many-core computing architecture. Graphical Processing Unit (GPU) is considered to be an essential innovation in this regard as GPU offers a significant amount of parallelism in the execution of complex computing applications. The performance of GPUs in reducing the computational time of such applications is worth mentioning. Although GPUs appear to be a problem-solving solution for complex applications yet high power consumption has been a challenging problem, associated with this many-core computer architecture. Efficient resource management is a emerging and promising solution to this challenge; however, reducing the resources would degrade the system's overall performance. On the other hand, reducing the resources based on the analysis of workload can save significant power without degrading the system's overall performance. Therefore, a smart controller to optimise the resources of general purpose-GPU (GP-GPU) architecture is required. AFBRMC-2, a neuro-fuzzy type-2 based controller, is presented for GP-GPU architecture and, based on a feedback mechanism, keeps analysing the stats of processor and manages resources using dynamic voltage frequency scaling and core gating techniques. The proposed controller achieved up to 55% reduction in power consumption against various benchmarks on the NVIDIA TK1 GPU kit.
One of the primary purposes of reliability evaluation is to identify and protect vulnerable components of a system. At the hardware level, the results of the evaluation can lead to design revisions that aim to increase the fault tolerance of the system. Every potential change is subject to validation and additionally requires more iterations of reliability evaluation. This back-and-forth process is expensive, especially when considering that hardware design changes require significant amounts of time to be applied. To address this problem, microarchitecture-level reliability assessment has been proposed. Instead of assessing the actual hardware design, the evaluation can be performed at microarchitecture-level (or performance) models that are often available very early in the design chain and are both flexible and allow high observability. The existence of reliability evaluation results before the actual design implementation enables early reliability-related design decisions and significantly decreases the cost of redesign cycles. But the absence of transistor-level detail on the evaluation inheritably results to some accuracy loss. Only components that are accurately modeled at the microarchitecture level, which are mostly memory elements (Static Random-Access Memory (SRAM) arrays, flops, and latches), can be assessed. Combinational logic and sequential elements are (in majority) functionally modeled, and thus, they cannot be evaluated at microarchitecture level. Fortunately, literature suggests that only a small portion (< 10%) of failures sources from these elements, which implies that the accuracy loss that can be attributed to the un-modeled resources at microarchitecture-level is limited. In this chapter, we present the throughput, capabilities, and accuracy of microarchitecturelevel reliability assessment, and how it can be effectively used at early design stages.
Reliability has always been a major concern in designing computing systems. However, the increasing complexity of such systems has led to a situation where efforts for assuring reliability have become extremely costly, both for the design of solutions for the mitigation of possible faults, and for the reliability assessment of such techniques. Cross-layer reliability is fast becoming the preferred solution. In a cross-layer resilient system, physical and circuit level techniques can mitigate low-level faults. Hardware redundancy can be used to manage errors at the hardware architecture layer. Eventually, software implemented error detection and correction mechanisms can manage those errors that escaped the lower layers of the stack. This book presents state-of-the-art solutions for increasing the resilience of computing systems, both at single levels of abstraction and multi-layers. The book begins by addressing design techniques to improve the resilience of computing systems, covering the logic layer, the architectural layer and the software layer. The second part of the book focuses on cross-layer resilience, including coverage of physical stress, reliability assessment approaches, fault injection at the ISA level, analytical modelling for cross-later resiliency, and stochastic methods. Cross-Layer Reliability of Computing Systems is a valuable resource for researchers, postgraduate students and professional computer architects focusing on the dependability of computing systems.
Exascale computing systems (ECS) are anticipated to perform at Exaflop speed (1018 operations per second) using power consumption <20 MW. This ultrascale performance requires the speedup in the system by thousand-fold enhancement in current Petascale. For future high-performance computing (HPC), power consumption is one of the vital challenges faced to achieve Exaflops through the traditional way of increasing clock-speed. One standard way to attain such significant performance is through massive parallelism. In the early stages, it is hard to decide the promising parallel programming approach that can provide massive parallelism to attain ExaFlops. This article commences with a short description and implementation of algorithms of various hybrid parallel programming models (PPMs) for homogeneous and heterogeneous cluster systems. Furthermore, the authors evaluated performance and power consumption in these hybrid models by implementing in two HPC benchmarking applications such as square matrix multiplication and Jacobi iterative solver for two-dimensional Laplace equation. The results demonstrated that the hybrid of heterogeneous (MPI + X) outperformed to homogeneous parallel programming (MPI + OpenMP) model. This empirical investigation of hybrid PPMs is a leading step for researchers and development communities to select a promising model for emerging ECS.
Smart cities are evolving globally and many governments have invested large sums of monies to develop smart cities. This development is not a result of an overnight decision but rather, smart cities have evolved through a period of time, directly from earlier work on the digital city to ubiquitous city, green city, connected city, sustainable city, eco-city etc. The present age sees the arrival of very high-speed wireless 5G connectivity, fast GPU multi-core-based servers, big data, cloud computing, artificial intelligence, and data analytics. Many of these new technologies have supported the development and realisation of smart cities. In this study, the authors present an outline of security for smart cities and provide a deeper understanding of what we meant by securing smart cities. They discuss the applicability of existing security methods of authentication, access control, encryption, firewalls, and their appropriateness to defending a smart city. Specifically, we cover the security of data, internet, water supply, electricity supply, city brain, and other critical city services and present the possible malicious attacks on a smart city and consequences. Finally, they discuss security best practices for smart cities.
This work presents an efficient approach for the generation of distributed Sparse Approximate Inverse preconditioners based on the near-field coupling information for the analysis of electromagnetic problems on large computing clusters. This scheme combines the Message Passing Interface and Open Multi-Processing paradigms in order to minimise the CPU time and memory footprint of the preconditioner, making use of specific algorithms tailored to balance the load and reduce the amount ot information shared between nodes. Some representative examples provide insight into the scalability and performance of the described approach addressing large and realistic scenarios.
Dependency on the correct operation of embedded systems is rapidly growing, mainly due to their wide range of applications. Their structures are becoming more complex and currently require multi-core processors with scalable shared memory, signal-processing pipelines, and sophisticated software modules to meet increasing computational power, flexibility demands. Additionally, interaction with real-world entities and modern communication capabilities further enhance the mentioned features and give rise to the embedded and cyber-physical systems (ECPS). As a consequence, the reliability of ECPS becomes a key issue during system development. Generally, state-of-the-art verification methodologies for ECPS generate test vectors and use assertion-based verification and high-level processor models, during simulation; however, new challenges arose, such as need for meeting time and energy constraints, handling concurrent software, evaluating implementation-structure choices, ensuring correct system behavior together with physical plants, and supporting new software architectures and legacy designs. This survey deals with the mentioned issues, reviews related literature, and discusses recent advances in symbolic model checking techniques and their applications to control synthesis. Additionally, challenges, problems, and recent advances to ensure correctness and timeliness, regarding ECPS, are discussed. Reliability issues, when developing ECPS, are then considered, as a prominent verification and synthesis application for achieving correct-by-construction systems.
For image matching, the scale invariant feature transform (SIFT) algorithm is a commonly used one. They are invariant to image rotation, scale zooming, and partially invariant to change in illumination and 3D camera viewpoint. Affine SIFT (ASIFT) is an extension of SIFT, which solves the problem when images are captured at different angles. However, ASIFT has higher computational complexity than SIFT, due to a huge amount of features in the images. Therefore, in this study, a Hadoop-based image retrieval system is proposed to solve the ASIFT shortcomings of high computation by the MapReduce technology. The system uses a combination of the Bag-of-Words method and support vector machine. Finally, the experimental results verify that the proposed method is more effective than the other state-of-the-art methods for a variety of datasets.
With successive scaling of CMOS technology, power density and cooling costs significantly increase. Consequently, the cooling system of processors can no longer be designed for the worst-case situation in each generation of CMOS technology and there is an essential need for run-time techniques to control the operating temperature. Task scheduling and resource management with respect to thermal constraints are run-time methods used to control the thermal profile of a system. In this study, the authors use Markov Reward Models (MRMs) to model and evaluate a new core thermal management method, which can reduce hotspots and balance the thermal profile of a multi-core system. Although the proposed management method degrades the performance of the system, such as other previously presented methods, it controls the temperature of a die to decrease the temperature variation and hotspots. The proposed approach is assessed on a quad-core system and the experimental results are compared to the results obtained from the proposed MRM to demonstrate the accuracy of the proposed analytical model.
Multiprocessors have become prevalent in real-time systems owing to their higher throughput. Various types of scheduling algorithms have been proposed for parallel real-time tasks, which differ from traditional tasks in that their subtasks execute in parallel. A parallel task is frequently modelled as a directed acyclic graph (DAG) that expresses the precedence constraints between its subtasks. In this Letter, the authors propose a decomposition algorithm to improve the Earliest Deadline First schedulability for DAG tasks, based on convex optimisation theory. Their experimental results demonstrate that their algorithm outperforms the two most recently published algorithms.
Devising energy-efficient scheduling strategies for real-time periodic tasks on heterogeneous platforms is a challenging as well as a computationally demanding problem. This study proposes a low-overhead heuristic strategy called, HEALERS, for dynamic voltage and frequency scaling (DVFS)-cum-dynamic power management (DPM) enabled energy-aware scheduling of a set of periodic tasks executing on a heterogeneous multi-core system. The presented strategy first applies deadline-partitioning to acquire a set of distinct time-slices. At any time-slice boundary, the following three-phase operations are applied to obtain a schedule for the next time-slice: first, it computes the fragments of the execution demands of all tasks onto each of the different processing cores in the platform. Next, it generates a schedule for each task on one or more processing cores such that the total execution demand of all tasks is satisfied. Finally, HEALERS applies DVFS and DPM on all processing cores so that energy consumption within the time-slice may be minimized while not jeopardising execution requirements of the scheduled tasks. Experimental results show that the proposed scheme is not only able to achieve appreciable energy savings with respect to state-of-the-art (5–42% on average) but also enables a significant improvement in resource utilisation (as high as 58%).
Thermal cycling, as well as spatial and thermal gradient, affects the lifetime reliability and performance of heterogeneous Multi-Processor Systems-on-Chips (MPSoCs). Conventional temperature management techniques are not intelligent enough to cater for performance, energy efficiency as well as the operating temperature of the system. In this study, the authors propose a light-weight novel thermal management mechanism (P-EdgeCoolingMode) in the form of intelligent software agent, which monitors and regulates the operating temperature of the CPU cores to improve the reliability of the system while catering for performance requirements. P-EdgeCoolingMode is capable of pro-actively monitoring performance and based on the user's demand the agent takes necessary action, making the proposed methodology highly suitable for implementation on existing as well as conceptual Edge devices utilising heterogeneous MPSoCs with dynamic voltage and frequency scaling (DVFS) capabilities. They validated the authors’ methodology on the Odroid-XU4 MPSoC and Huawei P20 Lite (HiSilicon Kirin 659 MPSoC). P-EdgeCoolingMode has been successful in reducing the operating temperature while improving performance and reducing power consumption for chosen test cases than the state-of-the-art. For applications with demanding performance requirement P-EdgeCoolingMode has been found to improve the power consumption by 30.62% at the most in comparison to existing state-of-the-art power management methodologies.
With the increase in processing cores performance have increased, but energy consumption and memory access latency have become a crucial factor in determining system performance. In tiled chip multiprocessor, tiles are interconnected using a network and different application runs in different tiles. Non-uniform load distribution of applications results in varying L1 cache usage pattern. Application with larger memory footprint uses most of its L1 cache. Prefetching on top of such application may cause cache pollution by evicting useful demand blocks from the cache. This generates further cache misses which increases the network traffic. Therefore, an inefficient prefetch block placement strategy may result in generating more traffic that may increase congestion and power consumption in the network. This also dampens the packet movement rate which increases miss penalty at the cores thereby affecting Average Memory Access Time (AMAT). The authors propose an energy-efficient caching strategy for prefetch blocks, ECAP. It uses the less used cache set of nearby tiles running light applications as virtual cache memories for the tiles running high applications to place the prefetch blocks. ECAP reduces AMAT, router and link power in NoC by 23.54%, 14.42%, and 27%, respectively as compared to the conventional prefetch placement technique.
For passive bistatic radar (PBR), it is convenient to use software method to realise the signal processing. However, because of the huge amount of data computing, it is difficult to achieve the real-time signal processing by software method only with server that uses CPU for calculation. To solve the problem, the PBR signal processing method with multi-CPUs based on pipeline processing is studied. The key point of the method is to improve the parallelism of the signal processing algorithm and to use all the CPU cores efficiently for parallel computing. The whole PBR signal processing is divided into several steps, such as clutter cancellation, correlation processing, CFAR detection and so on, and each step employs different CPU resources that contain many cores. The data processed in each steps is also divided into several pieces to fully use all the CPU cores. At last, the signal processing in software for digital television terrestrial broadcasting (DTTB) signal is achieved based on the method. The experiment is carried out to verify the method. In the experiment, the whole signal processing time for DTTB signal is much less than the time of signal to be processed, and the signal processing output is continuous.
A pipelined architecture is proposed in this work to speed up the point multiplication in elliptic curve cryptography (ECC). This is achieved, at first; by pipelining the arithmetic unit to reduce the critical path delay. Second, by reducing the number of clock cycles (latency), which is achieved through careful scheduling of computations involved in point addition and point doubling. These two factors thus, help in reducing the time for one point multiplication computation. On the other hand, the small area overhead for this design gives a higher throughput/area ratio. Consequently, the proposed architecture is synthesised on different FPGAs to compare with the state-of-the-art. The synthesis results over GF(2 m ) show that the proposed design can work up to a frequency of 369, 357 and 337 MHz when implemented for m = 163, 233 and 283 bit key lengths, respectively, on Virtex-7 FPGA. The corresponding throughput/slice figures are 42.22, 12.37 and 9.45, which outperform existing implementations.
Multicore processors are widely used in today's real-time embedded systems to satisfy the performance and predictability requirements as well as reduce cost. A vast majority of multicore embedded systems are running several tasks with mixed-criticality, in which the non-functional requirements of the tasks are different or even conflicting. A major challenge in mixed-criticality systems is to maximise the efficiency of shared resources while satisfying the criticality requirements. Shared memory is a key component that should be well managed and memory controller plays the main role in this case. Several memory controllers have been introduced in the literature for multicore processors. In this article, the authors performed a deep investigation on three state-of-the-art memory controllers using gem5 full-system simulator and Xilinx ISE Design Suite, and compared them in terms of predictability and performance. Then, the authors proposed a memory controller that provides the same predictability as the most predictable existing controller while improving the performance by 12.3%.
Parallelising transformations of Kahn process networks (KPNs) are important mechanisms for achieving speedup for deployment on heterogeneous multiprocessor systems particularly in the domain of signal processing applications. Correctness of such parallelising transformations is crucial for their reliable applications. In this study, verification frameworks for checking correctness of sequential to KPN behavioural transformation and KPN level transformations are presented. To the best of the authors’ knowledge, these are the first such approaches for verification problems. The sequential behaviour and the KPN behaviours are both modelled as array data dependence graphs (ADDGs) and the verification problem is posed as the problem of checking of equivalence between the two ADDGs. The key aspect of the proposed scheme is to model a KPN behaviour as an ADDG. Correctness of KPN to ADDG construction method is proved. Experimental results supporting usability of this scheme are also provided.
The Internet of Things (IoT) has recently emerged as an enabling technology for the next-generation electricity grid, namely, smart grid (SG). The efficient operation of the smart electricity grid depends on the efficient acquiring, analyzing, and processing of a large volume of data generated by the utilized smart sensors, individual smart meters, energy-consumption schedulers, aggregators, solar radiation sensors, wind-speed meters, and relays. In order to deal with the extreme size of data, the adoption of advanced data analytics, big data management, and powerful monitoring techniques is required. This approach creates huge opportunities and challenges, especially considering the real-time monitoring, load, renewable energy, and prices forecasting, identification and prediction of faults, and integration of electric vehicles, functioning in a mobile SG environment. Among others, intelligent algorithms, robust data analytics, high performance computing (HPC), efficient data network management, and cloud computing (CC) techniques are critical toward the optimized operation of SG. This chapter presents the big data issues faced by SG networks and the corresponding solutions.
Deep learning has been widely used in many software disciplines in both academia and industry including computer vision, speech recognition and translation, natural languages processing, search engine, bioinformatics, sensor data processing, finance, etc., due to its scalability in big data environments and accuracy at higher level than ever before. Especially, deep neural networks can utilize the parallel computational power of GPU to accelerate the learning process and ensure higher efficiency for big data problems.