Devising energy-efficient scheduling strategies for real-time periodic tasks on heterogeneous platforms is a challenging as well as a computationally demanding problem. This study proposes a low-overhead heuristic strategy called, HEALERS, for dynamic voltage and frequency scaling (DVFS)-cum-dynamic power management (DPM) enabled energy-aware scheduling of a set of periodic tasks executing on a heterogeneous multi-core system. The presented strategy first applies deadline-partitioning to acquire a set of distinct time-slices. At any time-slice boundary, the following three-phase operations are applied to obtain a schedule for the next time-slice: first, it computes the fragments of the execution demands of all tasks onto each of the different processing cores in the platform. Next, it generates a schedule for each task on one or more processing cores such that the total execution demand of all tasks is satisfied. Finally, HEALERS applies DVFS and DPM on all processing cores so that energy consumption within the time-slice may be minimized while not jeopardising execution requirements of the scheduled tasks. Experimental results show that the proposed scheme is not only able to achieve appreciable energy savings with respect to state-of-the-art (5–42% on average) but also enables a significant improvement in resource utilisation (as high as 58%).

With the increase in processing cores performance have increased, but energy consumption and memory access latency have become a crucial factor in determining system performance. In tiled chip multiprocessor, tiles are interconnected using a network and different application runs in different tiles. Non-uniform load distribution of applications results in varying L1 cache usage pattern. Application with larger memory footprint uses most of its L1 cache. Prefetching on top of such application may cause cache pollution by evicting useful demand blocks from the cache. This generates further cache misses which increases the network traffic. Therefore, an inefficient prefetch block placement strategy may result in generating more traffic that may increase congestion and power consumption in the network. This also dampens the packet movement rate which increases miss penalty at the cores thereby affecting Average Memory Access Time (AMAT). The authors propose an energy-efficient caching strategy for prefetch blocks, ECAP. It uses the less used cache set of nearby tiles running light applications as virtual cache memories for the tiles running high applications to place the prefetch blocks. ECAP reduces AMAT, router and link power in NoC by 23.54%, 14.42%, and 27%, respectively as compared to the conventional prefetch placement technique.

Multicore processors are widely used in today's real-time embedded systems to satisfy the performance and predictability requirements as well as reduce cost. A vast majority of multicore embedded systems are running several tasks with mixed-criticality, in which the non-functional requirements of the tasks are different or even conflicting. A major challenge in mixed-criticality systems is to maximise the efficiency of shared resources while satisfying the criticality requirements. Shared memory is a key component that should be well managed and memory controller plays the main role in this case. Several memory controllers have been introduced in the literature for multicore processors. In this article, the authors performed a deep investigation on three state-of-the-art memory controllers using gem5 full-system simulator and Xilinx ISE Design Suite, and compared them in terms of predictability and performance. Then, the authors proposed a memory controller that provides the same predictability as the most predictable existing controller while improving the performance by 12.3%.

The Internet of Things (IoT) has recently emerged as an enabling technology for the next-generation electricity grid, namely, smart grid (SG). The efficient operation of the smart electricity grid depends on the efficient acquiring, analyzing, and processing of a large volume of data generated by the utilized smart sensors, individual smart meters, energy-consumption schedulers, aggregators, solar radiation sensors, wind-speed meters, and relays. In order to deal with the extreme size of data, the adoption of advanced data analytics, big data management, and powerful monitoring techniques is required. This approach creates huge opportunities and challenges, especially considering the real-time monitoring, load, renewable energy, and prices forecasting, identification and prediction of faults, and integration of electric vehicles, functioning in a mobile SG environment. Among others, intelligent algorithms, robust data analytics, high performance computing (HPC), efficient data network management, and cloud computing (CC) techniques are critical toward the optimized operation of SG. This chapter presents the big data issues faced by SG networks and the corresponding solutions.

Power-efficient architectures have become the most important feature required for future embedded systems. Modern designs, like those released on mobile devices, reveal that clusterisation is the way to improve energy efficiency. However, such architectures are still limited by the memory subsystem (i.e. memory latency problems). This work investigates an alternative approach that exploits on-chip data locality to a large extent, through distributed shared memory systems that permit efficient reuse of on-chip mapped data in clusterised many-core architectures. First, this work reviews the current literature on memory allocations and explores the limitations of cluster-based many-core architectures. Then, several memory allocations are introduced and benchmarked scalability, performance and energy-wise against the conventional centralised shared memory solution in order to reveal which memory allocation is the most appropriate for future mobile architectures. The results show that distributed shared memory allocations bring performance gains and opportunities to reduce energy consumption.

Trade-offs between performance and power have dominated the processor architecture landscape in recent times and are expected to exert a considerable influence in the future. Processing technologies ceased to provide automatic speedups across generations, leading to the reliance on architectural innovation for achieving better performance. Manycore processor systems have found their way into various computing segments ranging from mobile systems to the desktop and server space. With the advent of graphics processing units (GPUs) with a large number of processing elements into the computing space, manycore systems have become the default engine for all target computing domains. We have focused in this chapter on mainly the desktop and system-on-chip (SoC) domain, but the architectural possibilities blend in a seamless way into the other domains also. We outline a high-level classification of manycore processors and go on to describe the major architectural components typically expected in modern and future processors, with a focus on the computing elements. Issues arising out of the integration of the various components are outlined. Future trends are also identified.

The chapter first gives a brief overview of how power is consumed in CPUs before exploring the various energy-saving techniques and power management considerations. A description of different power modelling approaches and applications is presented before top-down, run-time power models are described in detail, highlighting many important, but often-overlooked, considerations. Bottom-up approaches, their accuracy, and methods of improving their representativeness are then discussed and finally, hybrid approaches are proposed.

The current trends in building clusters and supercomputers are to use medium-to-big symmetric multi-processors (SMP) nodes connected through a high-speed network. Applications need to accommodate to these execution environments using distributed and shared memory programming, and thus become hybrid. Hybrid applications are written with two or more programming models, usually message passing interface (MPI) [1,2] for the distributed environment and OpenMP [3,4] for the shared memory support. The goal of this chapter is to show how the two programming models can be made interoperable and ease the work of the programmer. Thus, instead of asking the programmers to code optimizations targeting performance, it is possible to rely on the good interoperability between the programming models to achieve high performance. For example, instead of using non-blocking message passing and double buffering to achieve computation-communication overlap, our approach provides this feature by taskifying communications using OpenMP tasks [5,6].