ReRAM neural networks with focus on intensive matrix multiplication operations. ReRAM-crossbar network can be used as matrix-vector multiplication accelerator and then to illustrate the detailed mapping. The coupled ReRAM oscillator network can be applied for low-power and high-throughput L2-norm calculation. The 3D single-layer CMOS-ReRAM architecture will be used for tensorized neural network (TNN). A 3D multilayer CMOS-ReRAM architecture has advantages in three man-ifold. First, by utilizing ReRAM crossbar for input data storage, leakage power of memory is largely removed. In a 3D architecture with TSV interconnection, the bandwidth from this layer to next layer is sufficiently large to perform parallel computation. Second, ReRAM crossbar can be configured as computational units for the matrix-vector multiplication with high parallelism and low power. Lastly, with an additional layer of CMOS-ASIC, more complicated tasks such as division and non-linear mapping can be performed. As a result, the whole training process of ML can be fully mapped to the proposed 3D multilayer CMOS-ReRAM accelerator architecture towards real-time training and testing.

The categorisation of network packets according to multiple parameters such as sender and receiver addresses is called packet classification. Packet classification lies at the core of Software-Defined Networking (SDN)-based network applications. Due to the increasing speed of network traffic, there is an urgent need for packet classification at higher speeds. Although it is possible to accelerate packet classification algorithms through hardware implementation, this solution imposes high costs and offers limited development capacity. On the other hand, current software methods to solve this problem are relatively slow. A practical solution to this problem is to parallelise packet classification using multi-core processors. In this study, the Thread, parallel patterns library (PPL), open multi-processing (OpenMP), and threading building blocks (TBB) libraries are examined and implemented to parallelise three packet classification algorithms, i.e. tuple space search, tuple pruning search, and hierarchical tree. According to the results, the type of algorithm and rulesets may influence the performance of parallelisation libraries. In general, the TBB-based method shows the best performance among parallelisation libraries due to using a theft mechanism and can accelerate the classification process up to 8.3 times on a system with a quad-core processor.

To meet rising demands for computing resources, information technology service providers need to select cloud-based services for their vitality and elasticity. Enormous numbers of data centres are designed to meet customer needs. Burning up energy by data centre is very high with the large-scale deployment of cloud data centres. Virtual machine consolidation strategy implementation reduces the data centre energy consumption and guarantees service level agreements. This study proposes a machine learning-based method in cloud computing for the automated use of virtual machines. Machine learning-based virtual machine selection approach integrates the migration control mechanism that enhances selection strategy efficiency. The experiment is performed with various real machine workload circumstances to provide proof and effectiveness of the proposed method. The exploratory outcome shows that the proposed approach streamlines the utilisation of the virtual machine and diminishes the consumption of energy and improves infringement of service level agreements to accomplish better performance.

Geometric primitives contained in three-dimensional (3D) point clouds can provide the meaningful and concise abstraction of 3D data, which plays a vital role in improving 3D vision-based intelligent applications. However, how to efficiently and robustly extract multiple geometric primitives from point clouds is still a challenge, especially when multiple instances of multiple classes of geometric primitives are present. In this study, a novel energy minimisation-based algorithm for multi-class multi-instance geometric primitives extraction from the 3D point cloud is proposed. First, an improved sampling strategy is proposed to generate model hypotheses. Then, an improved strategy to establish the neighbourhood is proposed to help construct and optimise an energy function for points labelling. After that, hypotheses and parameters of models are refined. Iterate this process until the energy does not decrease. Finally, models of multi-class multi-instance geometric primitives are simultaneously and robustly extracted from the 3D point cloud. In comparison with the state-of-the-art methods, it can automatically determine the classes and numbers of geometric primitives in the 3D point cloud. Experimental results with synthetic and real data validate the proposed algorithm.

One of the primary purposes of reliability evaluation is to identify and protect vulnerable components of a system. At the hardware level, the results of the evaluation can lead to design revisions that aim to increase the fault tolerance of the system. Every potential change is subject to validation and additionally requires more iterations of reliability evaluation. This back-and-forth process is expensive, especially when considering that hardware design changes require significant amounts of time to be applied. To address this problem, microarchitecture-level reliability assessment has been proposed. Instead of assessing the actual hardware design, the evaluation can be performed at microarchitecture-level (or performance) models that are often available very early in the design chain and are both flexible and allow high observability. The existence of reliability evaluation results before the actual design implementation enables early reliability-related design decisions and significantly decreases the cost of redesign cycles. But the absence of transistor-level detail on the evaluation inheritably results to some accuracy loss. Only components that are accurately modeled at the microarchitecture level, which are mostly memory elements (Static Random-Access Memory (SRAM) arrays, flops, and latches), can be assessed. Combinational logic and sequential elements are (in majority) functionally modeled, and thus, they cannot be evaluated at microarchitecture level. Fortunately, literature suggests that only a small portion (< 10%) of failures sources from these elements, which implies that the accuracy loss that can be attributed to the un-modeled resources at microarchitecture-level is limited. In this chapter, we present the throughput, capabilities, and accuracy of microarchitecturelevel reliability assessment, and how it can be effectively used at early design stages.

Reliability has always been a major concern in designing computing systems. However, the increasing complexity of such systems has led to a situation where efforts for assuring reliability have become extremely costly, both for the design of solutions for the mitigation of possible faults, and for the reliability assessment of such techniques. Cross-layer reliability is fast becoming the preferred solution. In a cross-layer resilient system, physical and circuit level techniques can mitigate low-level faults. Hardware redundancy can be used to manage errors at the hardware architecture layer. Eventually, software implemented error detection and correction mechanisms can manage those errors that escaped the lower layers of the stack. This book presents state-of-the-art solutions for increasing the resilience of computing systems, both at single levels of abstraction and multi-layers. The book begins by addressing design techniques to improve the resilience of computing systems, covering the logic layer, the architectural layer and the software layer. The second part of the book focuses on cross-layer resilience, including coverage of physical stress, reliability assessment approaches, fault injection at the ISA level, analytical modelling for cross-later resiliency, and stochastic methods. Cross-Layer Reliability of Computing Systems is a valuable resource for researchers, postgraduate students and professional computer architects focusing on the dependability of computing systems.

Fog computing is a decentralised model which can help cloud computing for providing high quality-of-service (QoS) for the Internet of Things (IoT) application services. Service placement problem (SPP) is the mapping of services among fog and cloud resources. It plays a vital role in response time and energy consumption in fog–cloud environments. However, providing an efficient solution to this problem is a challenging task due to difficulties such as different requirements of services, limited computing resources, different delay, and power consumption profile of devices in fog domain. Motivated by this, in this study, we propose an efficient policy, called MinRE, for SPP in fog–cloud systems. To provide both QoS for IoT services and energy efficiency for fog service providers, we classify services into two categories: critical services and normal ones. For critical services, we propose MinRes, which aims to minimise response time, and for normal ones, we propose MinEng, whose goal is reducing the energy consumption of fog environment. Our extensive simulation experiments show that our policy improves the energy consumption up to 18%, the percentage of deadline satisfied services up to 14% and the average response time up to 10% in comparison with the second-best results.

This Letter reports a method to obtain fine-grained energy consumption analysis of programs running on the low-power internet of things (IoT) devices. In the energy estimation domain, most state-of-the-art solutions focus on the coarse-grained approach to monitor the energy consumption of a device or an application. However, few solutions addressed energy monitoring to analyse fine-grained energy consumption of a program, especially for IoT appliances. Therefore, the authors present a fine-grained gem5-based energy profiling tool to help developers to evaluate the energy efficiency of hot spots in their programs. The authors demonstrate its usability by applying it to profiling garbage collection and property lookup in Jerryscript, a JavaScript engine specifically designed for resource-constrained IoT devices, and discover that these two operations are consuming, as they account for 17.67 and 12.26% of total energy, respectively. Therefore, this tool can aid the developers to gain insight into the energy efficiency of their software.

Mobile edge computing (MEC) is an effective assistant technology that can overcome some defects of cloud computing. For the sake of alleviating the clashes between the capability constraint of cloudlets and the needs of mobile devices (MDs) for reducing executing latency as well as decreasing the power consumption of MDs, a user-oriented use case in the MEC named computation offloading is taken into consideration. Computation offloading is capable of effectively making the MEC adapt to the resources of cloudlets and MDs in different environments, and it is very beneficial to the development of the internet of things. Owing to the finite computation capabilities of the MDs and the resources of cloudlets are heterogeneous and limited; a three-objective model is established to optimise the time consumption, and the energy consumption of MDs as well as the load balancing of cloudlets jointly. Technically, the authors propose an effective multi-user multi-application computation offloading method in the multi-cloudlet environment on the basis of improved non-dominated sorting genetic algorithm III. Finally, comprehensive experiments and analysis were conducted to validate the effectiveness and efficiency of the proposed method.

Flash controller is the core hardware embedded in today's mobile device storage, and the flash translation layer (FTL) is the key system of controller. This Letter proposes a high-efficient superblock FTL (HSPB) to satisfy the demand of large media files and application files storage, which implements the cross-block sequential writing strategy and the shared cached mapping table scheme. Test results show that HSPB reduces the time and power consumption by 7–30% in seq/random write and gains up to 60% improvement in sequential/random read compared to other FTLs.