A novel fault tolerant delay cell for ring oscillator (RO) is proposed. As RO is one of the crucial blocks in phased locked loop, delayed locked loo and clock data recovery, it should be tolerated against single event transient (SET) and stuck at faults for harsh environment. Their proposed hybrid fault tolerant topology is combination of triple and quad transistors redundancy, which is applied to the delay cell structure based on the sensitivity role of each transistor. The simulation results with Cadence software show that the proposed fault-tolerant delay cell dissipates 34.34 µW power, while it occupies 127.2 µm² chip area. The proposed topology not only has lower power dissipation in comparison with existing fault tolerant delay cells but also is more reliable against stuck at single and multiple faults and also SETs. By using the proposed reliable delay cell in the RO, the achieved power dissipation and phase noise are about 249 µW and −96 dBc/Hz, respectively, while higher reliability is achieved in comparison with non-redundant RO s.

Field programmable gate array (FPGA) attributes of logic configurability, bitstream storage, and dynamic signal routing can be realised by leveraging the complementary benefits of emerging devices with complementary metal oxide semiconductor (CMOS)-based devices. A novel carbon/magnet lookup table (CM-LUT) is developed and evaluated by trading off a range of mixed heterogeneous technologies to balance energy, delay, and reliability attributes. Herein, magnetic spintronic devices are employed in the configuration memory to contribute non-volatility and high scalability. Meanwhile, carbon nanotube field-effect transistors (CNFETs) provide desirable conductivity, low delay, and low power consumption. The proposed CM-LUT offers ultra-low power and high-speed operation while maintaining high endurance re-programmability with increased radiation-induced soft-error immunity. The proposed four-input one-output CM-LUT utilises 41 CNFETs and 20 magnetic tunnel junctions for read operations and 35 CNFET to perform write operations. Results indicate that CM-LUT achieves an average four-fold energy reduction, eight-fold faster circuit operation and 9.3% reconfiguration power delay product improvement in comparison with spin-based look-up tables. Finally, additional hybrid technology designs are considered to balance performance with the demands of energy consumption for near-threshold operation.

Power metal-oxide semiconductor field-effect transistors (MOSFETs) are increasingly used in the space probes where the environment is composed of various kinds of particles. Thus, it is essential to study the influence of the natural radiation environment on the electrical behaviour of MOSFETs in space. This study presents two-dimensional numerical simulation results, which investigates the sensitive volume, triggering criteria and characteristics of single-event burnout (SEB) and single-event gate rupture (SEGR) for the split-gate enhanced power U-shape MOSFET (SGE-UMOS). In addition, the comparison of the standard Trench-UMOS and SGE-UMOS for both SEB and SEGR simulation results is investigated. The SGE-UMOS shows an improved SEB performance than the standard Trench-UMOS with a larger safe operating area. The SGE-UMOS can also contribute to protect against SEGR compared with standard Trench-UMOS.

The authors investigated the performance of ZnO nanowire-based metal–semiconductor field effect transistors (MESFETs) by focusing electron beam on the Schottky gate. The MESFET was fabricated by employing Tantalum as drain and source and by using Schottky barrier at tungsten–ZnO interface as the gate. As to I_DS against V_GS curves, once the gate was illuminated with electron beam radiation, crests with a redshift as V_DS increased and a p-type semiconductor transistor behaviour were observed. At the critical points, the value of V_DS−V_GS revealed a linear behaviour with the increasing V_DS. The authors attributed these results to the gain enhanced by electron beam radiation and carrier-trapping process, while the shift may be associated with the image-force lowing effect.

The effect of excess donor doping introduced by implantation with 700 kV and 1.8 MeV protons and subsequent annealing up to 550°C in silicon substrates with different oxygen content was investigated. Three different types of silicon material were chosen for this purpose: Czochralski, oxygen-lean and oxygen rich float-zone silicon. Deep and shallow levels resulted from implantation and subsequent annealing were studied by deep level transient spectroscopy and C-Vprofiling. Results show that hydrogen donors appear at the proton end-of-range after implantation in all materials. Their introduction rate depends linearly on proton fluence and is substantially higher in Czochralski and oxygen-rich float zone materials due to higher oxygen concentration. It is shown that during post-implantation annealing, the excess donor doping changes in several phases. Hydrogen donors anneal out above 250°C and then, hydrogen-related thermal donors and thermal donors are generated. When annealing temperature exceeds 400°C, the hydrogen thermal donors are still localized at the proton end-of-range in oxygen-lean float zone silicon while in Czochralski silicon and oxygen-rich float zone material, thermal donors arise in the whole bulk and radiation enhanced thermal donors decorate the profile of radiation damage. The level of local doping by hydrogen thermal donors is proportional to implantation fluence and layers are stable up to 550°C for implantation fluences above 10¹³ cm^-2 . The detrimental effect of hydrogen donors and thermally activated donors on blocking characteristics of power p⁺nn⁺ diodes is also discussed.

The influence of annealing temperature (700, 800°C) and implantation dose (1 × 10¹³ - 1 × 10¹⁴ cm^-2 ) of 9.5 MeV Pd on the subsequent Radiation Enhanced Diffusion (RED) is studied in the range of optimal diffusion temperatures (550, 600, 650°C)for the electrical parameters of a power P-I-N diode. Spreading resistance measurements have shown that the Pd dose of 1 × 10¹⁴ cm^-2 is capable to compensate the anode doping profile in the N-base close to the anode junction similar to that of the RED from sputtered Pd. Contrary to the devices with sputtered Pd, the reproducibility of this process is lower and the radiation damage from the Pd implantation compensates the high doped P layer up to the Pd range (≈ 3.5 μm). The dependences of leakage, carrier lifetime, forward voltage drop and reverse recovery on the process parameters of the Pd layer are shown for 2.5 kV/100 A diode.

A substantial reduction of the leakage current in 4H-SiC pin diodes is observed after <10 eV UV irradiation in air. The high energy UV is believed to remove carbon clusters from the SiC surface. Comparison of leakage current in 4H-SiC pin diodes after different surface treatments, including reactive ion etching, exposure to two different sources of UV light and different forms of chemical cleaning, is presented. Exposure to 4.9 eV UV light in nitrogen atmosphere enhances the leakage by one order of magnitude.

The back channel low-frequency noise of 1.2 μm×2.3 μm SOI nMOS transistors with a buried oxide thickness of 170 nm was measured as a function of frequency, back gate bias V_bg and temperature T. For a temperature range of 85≤T≤320 K, noise measurements were performed at frequencies of 0.3≤f≤1 kHz with top gate bias V_bg=0 V and V_bg−V_bg−th=4 V, where V_bg−th is the back gate threshold voltage. The temperature and frequency dependences of the 1/f noise of back channel SOI nMOS transistors show thermally activated charge exchange between the Si channel and defects in the buried oxide. Comparison is made with the Dutta and Horn model of 1/f noise. Devices on one particular wafer appear to show a mixture of 1/f noise and noise with a higher frequency exponent at low temperatures. Little change is observed in back gate noise with irradiation for the devices and irradiation conditions studied. This is probably due to large preirradiation defect densities in the buried oxides.

The effects of pre-irradiation gate bias stress on the radiation response of power VDMOSFETs are presented, clearly demonstrating the inapplicability of gate bias stressing as a technique for radiation hardening of power MOSFETs.

The authors demonstrate high-performance AlGaN/GaN heterostructure field-effect transistors (HFETs) with mesa isolation achieved by a recently developed UV-assisted, batch processing compatible, wet etching process. HFETs with a 0.2 µm gate feature peak cutoff frequencies of f_T = 43 GHz and f_MAX = 98 GHz for a piezoelectric HFET grown on a sapphire substrate by molecular beam epitaxy. The transistors feature low gate diode leakage currents and display no sensitivity to visible light.

The triggering mechanism for cosmic ray neutron-induced single-event burnout (SEB) in silicon insulated-gate bipolar transistors (IGBTs) and diodes was investigated by white neutron-irradiation experiments and transient device simulations. Electron-hole pairs are generated along the tracks of recoil ions produced by nuclear spallation reactions between incident neutrons and the constituent nuclei of the device. In the vicinity of the n⁻/n⁺ interface, the resulting dynamic current causes an increase in the electron density, and the space charge effect of the carriers leads to an increase in the peak electric field. In an IGBT, the onset of impact ionisation at this interface can cause a parasitic transistor to switch on. In the case of diodes, the electric field distribution leads to diode secondary breakdown. Therefore, impact ionisation at the n⁻/n⁺ interface is essential for triggering SEB. In this study, analytical equations are derived for the local rise in temperature during SEB. The local temperature rise is proportional to the energy, defined in terms of the product of the applied voltage and the total avalanche charge. The diameter of the damage region estimated using these equations is similar to the size of the observed annular voids.