Digital storage
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- Electrical and electronic engineering [12]
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- http://iet.metastore.ingenta.com/content/subject/b2500,http://iet.metastore.ingenta.com/content/subject/b2570,http://iet.metastore.ingenta.com/content/subject/b2570d,http://iet.metastore.ingenta.com/content/subject/c5100,http://iet.metastore.ingenta.com/content/subject/c7000,http://iet.metastore.ingenta.com/content/subject/c7400,http://iet.metastore.ingenta.com/content/subject/c7410,http://iet.metastore.ingenta.com/content/subject/b1265b,http://iet.metastore.ingenta.com/content/subject/b1265f,http://iet.metastore.ingenta.com/content/subject/b6000,http://iet.metastore.ingenta.com/content/subject/c1000,http://iet.metastore.ingenta.com/content/subject/c5120,http://iet.metastore.ingenta.com/content/subject/c5320c,http://iet.metastore.ingenta.com/content/subject/b0000,http://iet.metastore.ingenta.com/content/subject/b0200,http://iet.metastore.ingenta.com/content/subject/b0240,http://iet.metastore.ingenta.com/content/subject/b0240z,http://iet.metastore.ingenta.com/content/subject/b1100,http://iet.metastore.ingenta.com/content/subject/b1130,http://iet.metastore.ingenta.com/content/subject/b1130b,http://iet.metastore.ingenta.com/content/subject/b1220,http://iet.metastore.ingenta.com/content/subject/b1230,http://iet.metastore.ingenta.com/content/subject/b1230j,http://iet.metastore.ingenta.com/content/subject/b1265z,http://iet.metastore.ingenta.com/content/subject/b1270,http://iet.metastore.ingenta.com/content/subject/b1270e,http://iet.metastore.ingenta.com/content/subject/b2570f,http://iet.metastore.ingenta.com/content/subject/b3000,http://iet.metastore.ingenta.com/content/subject/b3100,http://iet.metastore.ingenta.com/content/subject/b3120,http://iet.metastore.ingenta.com/content/subject/b3120b,http://iet.metastore.ingenta.com/content/subject/b5000,http://iet.metastore.ingenta.com/content/subject/b5200,http://iet.metastore.ingenta.com/content/subject/b5230,http://iet.metastore.ingenta.com/content/subject/b6100,http://iet.metastore.ingenta.com/content/subject/b6120,http://iet.metastore.ingenta.com/content/subject/b6120b,http://iet.metastore.ingenta.com/content/subject/b6200,http://iet.metastore.ingenta.com/content/subject/b6230,http://iet.metastore.ingenta.com/content/subject/b6230b,http://iet.metastore.ingenta.com/content/subject/b8000,http://iet.metastore.ingenta.com/content/subject/b8300,http://iet.metastore.ingenta.com/content/subject/b8360,http://iet.metastore.ingenta.com/content/subject/c1100,http://iet.metastore.ingenta.com/content/subject/c1140,http://iet.metastore.ingenta.com/content/subject/c1140z,http://iet.metastore.ingenta.com/content/subject/c1300,http://iet.metastore.ingenta.com/content/subject/c1310,http://iet.metastore.ingenta.com/content/subject/c3000,http://iet.metastore.ingenta.com/content/subject/c3100,http://iet.metastore.ingenta.com/content/subject/c3110,http://iet.metastore.ingenta.com/content/subject/c3110b,http://iet.metastore.ingenta.com/content/subject/c3110d,http://iet.metastore.ingenta.com/content/subject/c3300,http://iet.metastore.ingenta.com/content/subject/c3340,http://iet.metastore.ingenta.com/content/subject/c3340h,http://iet.metastore.ingenta.com/content/subject/c5130,http://iet.metastore.ingenta.com/content/subject/c5135,http://iet.metastore.ingenta.com/content/subject/c5310,http://iet.metastore.ingenta.com/content/subject/c5400,http://iet.metastore.ingenta.com/content/subject/c5470,http://iet.metastore.ingenta.com/content/subject/c6000,http://iet.metastore.ingenta.com/content/subject/c6100,http://iet.metastore.ingenta.com/content/subject/c6110,http://iet.metastore.ingenta.com/content/subject/c6130,http://iet.metastore.ingenta.com/content/subject/c7410b,http://iet.metastore.ingenta.com/content/subject/c7410d,http://iet.metastore.ingenta.com/content/subject/c7410f,http://iet.metastore.ingenta.com/content/subject/c7420
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- 1998 [12]
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A rather simple ROM-based current controller is proposed for a three-phase boost-type AC/DC converter to achieve a clean sinusoidal input current, controllable power factor, an adjustable DC voltage, a bidirectional power flow capability, a fixed switching frequency and one insensitive to input voltage distortion. Three control schemes are proposed and integrated in the same controller. As well as the basic scheme, there are a further two choices for either reducing almost half the switch loss or enhancing the availability of the converter, while one arm of the converter fails. A prototype is constructed, and experimental results validate the simulated results.
A complementary half-swing bus architecture is proposed for high speed and low power operation. The bus is composed of pairs of lines. The bus operates with three steps every cycle. In the first two steps, both bus lines within a pair are set at a half of the supply voltage. In the last step, each bus level is determined independently according to their data whether it is driven to the supply voltage or ground level, or remains unchanged. Then, each bus line swings the upper or lower half of the supply voltage exclusively. This simple architecture is able to transfer data in mutual direction at higher speed without an area penalty. It is applied to an SRAM macro with 112-bit bus for an ATM switch LSI. The 84 K-bit macro is fabricated in an area of 3.5 mm × 4.2 mm with a 0.5 µm CMOS process technology. Experimental results indicate that it operates beyond 200 MHz at the supply voltage of 3.3 V. From a cross-talk consideration, the cross-talk works such as to enlarge the operation margin. Simulation results show that the worst case power dissipation and the peak current due to simultaneous switching are reduced by half and by 66%, respectively, compared with full swing architectures.
A two-phase back-bias (VBB) generator is proposed for use in gigabit DRAMs using triple-well CMOS technology. The lower limit of VCC for the proposed VBB generator is a single VT (threshold voltage), whereas that for the conventional VBB generator is 2·VT.
A new charge transfer preamplifier scheme is developed for low power and high density DRAMs. It employs a boosting method with a MOSFET capacitor for a high voltage precharge level and a pulse control signal for a charge transfer switch. The new scheme increases the sensing margin and enhances the sensing speed under 1.5 V operation with a small area overhead. It also leads to a wider design window for a charge transfer switch as the supply voltage scales down.
Digital signal processors implement modulo addressing by using separate hardware generation and comparison. To simplify hardware, they restrict the starting address, the displacement value, and/or the buffer length. The authors show that, by rewriting the equations for modulo addressing, it is possible to combine address generation and comparison to simplify hardware without loss in speed.
A new multiple twisted data line technique to reduce both bit-line and word-line coupling noises is proposed and demonstrated. An improved noise/signal ratio resulting from the application of the proposed technique is confirmed by soft-error rate tests. A faster data access time can also be expected when the proposed technique is incorporated into dynamic random access memories.
Area-efficient architectures for integrated N-port memories employ blocks of one port memory cells and dynamic port-to-block connections. The authors determine the block number M necessary to achieve a target port-access-rejection probability for a given port number N and best-case/worst-case conflict-resolve algorithms, by applying stochastic probability theory.
A novel low-voltage current conveyor for fast CMOS SRAM applications is presented. The sensing speed is independent of the bit-line capacitances and a positive feedback technique is employed to give the circuit a high-speed and low-power operation. Performance evaluation has shown that, based on equal area ratios, the new conveyor outperforms the conventional circuit in terms of speed and average power dissipation by at least 30%. The static behaviour of the basic circuit is analysed, and HSPICE simulations have been used to characterise the circuits. Experimental results have verified the functionality of the new circuit and its superiority over the conventional CMOS current conveyor.
A simple and novel nonvolatile SRAM (NVSRAM) cell is proposed. The NVSRAM cell can be achieved by adding only one nonvolatile device with split floating gates to a conventional SRAM cell. It acts as a conventional SRAM cell under normal operation. SRAM cell data are programmed to the nonvolatile device by hot electron injection. At power up, data are restored using different capacitance loading resulting from the split floating gate. The operations have been confirmed by circuit simulation. The NVSRAM cell is symmetric, and therefore has better retention characteristics than other NVSRAM cells.
Presents a hardware implementation of the Fitzpatrick algorithm (denoted by F) for solving the key equation in Reed-Solomon decoding. In addition, comparisons with the Berlekamp Massey (denoted by BM) algorithm in terms of area (FPGA resources) and speed are made. It is shown that use of the division free F algorithm results in both area and speed improvements in PRML systems. (5 pages)
Small, serial Electrically Erasable memories (EEPROMs) are widely used in many types of electronic products. They offer non-volatile storage for a small amount of data, take up little space, and are generally easy to use. The author has experience of using these devices in a range of industrial control and telemetry products. Typically these are used for signal conditioning, processing and transmission, control of actuators and so forth. Permanent memory storage is required for calibration parameters, mode and setup parameters. These may be entered either from the product's own user interface, or via a serial part either from the control system (if there is one), or with a local terminal. The products with which the author has been associated have had some in-house testing with regard to electromagnetic interference and power supply interruptions. This testing has not revealed problems with respect to EEPROMs. (4 pages)
A 400 Mbps, 1394 Disk Controller IC, with 0.75 Mbits of integrated DRAM, in a 0.35 μm 5 layer metal CMOS ASIC process is presented. The device makes use of a variety of circuit techniques, to achieve 5 V tolerance, and low jitter clock generation as well as 40 MIPs operation for the embedded RISC. The device provides a flexible architecture which can be easily extended to 800+ Mbps by integrating the 1394 physical layer (PHY) transceivers. (2 pages)
