A swap time-aware garbage collection (STGC) policy for the NAND flash-based swap system is proposed, which focuses on reducing the cleaning cost and improving the degree of wear-levelling. STGC calculates the cleaning index value of each block to select a victim block and the normalised value of the elapsed swap time of each valid page within the victim blocks to identify the hot valid page and cold valid page. Trace-driven simulations with a synthetic trace show that the STGC outperforms the existing garbage collection policies.

Design and implementation of a fully table look-up digital pulse-width modulation (DPWM) controller for high-frequency DC–DC buck conversion is presented. The controller comprises a 1 bit analogue comparator, a digital error process unit and a fully table look-up multi-phase DPWM. The interface of analogue-to-digital conversion is performed with the analogue comparator. Moreover, the proposed programmable memory is based on the table look-up multi-phase approach for the functions of the proportional-integral-derivative (PID) compensation, which alleviates the penalty of using large chip-area multipliers. As a result, the approach is very suitable for system-on-a-chip (SOC) implementation. A prototype test chip is realised to validate the mechanism of the proposed architecture.

A design for an integer motion estimator of high-efficiency video coding (HEVC) is presented. HEVC supports the 64 × 64 coding tree unit, the recursive quad-tree coding unit structure and the asymmetric motion-partitioning mode in a high compression ratio. These features require a structure of integer motion estimation that is more complex than that of H.264/AVC. The new structures of a memory read controller and a sum of absolute difference (SAD) summation block are proposed. The new memory read controller reduces the internal memory read time, and the new SAD summation block structure supports the recursive quad-tree coding unit structure and the asymmetric motion-partitioning mode. The proposed design is implemented in Verilog HDL and synthesised using the 65 nm CMOS technology. The gate count is 3.56 M, and the internal static random access memory is about 20 kbyte. The operation frequency is 250 MHz when a 4 K-Ultra high definition (UHD) (3840 × 2160P at 30 Hz) sized video is encoded.

As an implementation of the static random access memory (SRAM), the tunnelling SRAM (TSRAM) uses the negative differential resistance of resonant (interband) tunnelling diodes (R(I)TDs) and potentially offers improved standby power dissipation and integration density compared with the conventional CMOS SRAM. TSRAM has not yet been realised with a useful bit capacity mainly because the level of reproducibility required of the nanoscale R(I)TDs has been demanding and difficult to achieve. In this reported work, the design of TSRAM cells is approached from the perspective of maximising their yield and specific results are presented for an RITD-based cell. With advances in the control of semiconductor multilayer growth, it is shown that achieving acceptable yields is now within sight.

To reduce the reset current for developing reliable high-density phase change random access memory, small bottom electrode contact (BEC) size formation is a critical process. One of the failure modes for the process is the corrosion of the tungsten (W) plug, which is caused by the W chemical mechanical polisher (CMP) process. An ultra-smooth surface of BEC nanoscale W plug structure was successfully fabricated by the CMP process, which reduced the W/phase change material (Ge2Sb2Te5, GST) contact resistance, and gained more homogeneous resistance distribution. Thus, the stability of the device was improved greatly by the acidic buff CMP process compared with that of the device with alkali buff owing to the reduction of W/GST connect resistance fluctuation.

In-network caching leveraged in information-centric networking (ICN) is one key difference between ICN and the current Internet. Taken into account the complexity and practicality of technology, cooperatively in-network caching is yet so far. However, caching efficiency of current uncooperative caching scheme is disappointing. Network coding is considered as the most promising information theoretic approach to improve performance in current Internet. The authors’ previous work has proposed information-centric networking built network coding (ICN-NC). In this study, the authors will prove that ICN-NC can also improve caching efficiency besides network performance. First, a theoretical model is proposed to evaluate caching efficiency of ICN and ICN-NC, and compare the caching efficiency between ICN and ICN-NC both analytically and by simulations. Then effect of different parameters on caching efficiency, such as file size, copy size and probability of replacement etc., are also extensively researched. Furthermore, the authors formulate the overall caching efficiency as a multi-objective optimisation problem with constraints, and then Pareto optimal set to achieve an optimal allocation of network-wide caching is obtained.

The fabrication of gallium oxide nanodots for the application of resistive random access memory (RRAM) using a process of atomic force microscopy (AFM) local anodic oxidation on an indium tin oxide conductive glass substrate is reported. In the atmospheric environment, an AFM probe tip contacts the gallium film locally. This gallium oxide nanodot acts as the insulator layer in a single unit of the RRAM. The structure describes the insulator layer (GaOx) sandwiched by the top (AFM tip) and bottom (Ga film) electrodes. Using current and voltage biased methods, the device switches from a high-resistance state (HRS) to a low-resistance state (LRS) and reset from LRS to HRS. Low read-voltage is used to distinguish the high/low resistance to present the digital data. Presented results show the ability of atomic force microscopy anodic oxidation to produce 300 nm diameter gallium oxide nanodots on glass substrates for potentially high density RRAMs.