To increase storage capacity and I/O bandwidth, modern solid-state drives embed multiple NAND packages that consist of one or multiple dies in a parallel architecture. Each die can process NAND read/write/erase operations independently. A dynamic die binding method for write requests that is intended to exploit this parallel processing capability is proposed. This scheme stripes data to idle dies first, and unlike existing dynamic binding schemes, when idle dies are lacking it selects dies with the lowest accumulated write loads, thereby achieving wear levelling by ensuring long-term write load balancing. Thus, it can prevent situations in which some dies are worn out more quickly than others. A performance evaluation demonstrates that our approach offers slightly better performance compared with an existing dynamic binding scheme and completely resolves the problem of imbalanced write loads.

With the advent of multiple cores on a single chip, it is common for the systems to have multi-level caches. Multiple levels of cache reduce the pressure on the memory bandwidth by allowing applications to store their frequently accessed data in them. The levels of cache nearer to the core filter the locality in the application access, which can result in high miss rates at farther levels. This piece of study revolves around one question: are all levels of cache needed by all applications during all phases of their execution? The study observes the effect of 2-level and 3-level cache hierarchies on the performance of different applications. On the basis of this study, this study proposes an application aware cache management policy called ‘SkipCache’, which allows an application to choose a 2-level or 3-level cache hierarchy during run-time. SkipCache dynamically tracks the applications at shared last-level cache (LLC) to identify the applications that do not obtain advantage by using the LLC. Such applications can completely skip the LLC so that other co-scheduled cache friendly applications can efficiently use it. Evaluation of SkipCache in a 4-core chip multi-processor with multi-programmed workloads shows significant performance improvement. SkipCache is orthogonal to other cache management techniques and can be used along with other optimisation techniques to improve the system performance.

Quantum dot gate field-effect transistor (QDGFET) generates three states in their transfer characteristics. A successful model can explain the generation of third state in the transfer characteristics of the QDGFET. The innovative circuit design using QDGFET can be used to design different ternary logic. This Letter discusses the design of ternary logic static random access memory using QDGFET.

In this paper, a new voltage mirror circuit by using carbon nanotubes (CNTs) technology is presented. This circuit is specifically proposed for the application of duplicating multiple-valued and fuzzy dynamic random access memories. The given structure prevents any voltage drop for the capacitor inside the memory cell. As a result, any fanout circuit can be driven. The new structure can be utilised for different multiple-valued logic systems without a change. The unique characteristics of carbon nanotube field effect transistor (CNFET) technology are exploited in this paper to meet the desired design goals. It demonstrates the potentials of CNFET technology in a realistic very large-scale integration application. The proposed design is highly tolerant to D _CNT variation and it is also immune to misaligned CNTs. Simulation results demonstrate that it provides sufficient driving capability with reasonable accuracy.

An efficient replica bitline (RBL) technique for reducing the variation of sense amplifier enable (SAE) timing is proposed. Both RBLs and four-fold replica cells compared with the conventional RBL technique are utilised to favour the desired operations. Simulation results show that the standard deviation of SAE can be suppressed by 44.25% and the cycle time is also reduced by ∼30% at a 0.8 V supply voltage in TSMC 65 nm technology. Additionally, the area of the proposed scheme is nearly the same as that of the conventional RBL scheme.

A low-cost memory data scheduling method based on two N/2-depth single-port memories is proposed for reconfigurable fast Fourier transform (FFT) bit-reversed data reordering tasks. To make single-port memories have the equivalent ability to read and write data simultaneously, two types of read and write address generation methods are proposed. Based on the proposed data scheduling method, the bit-reversal circuits are designed for continuous data reordering tasks. The proposed bit-reversal design is implemented for a maximum 8 k flexible length FFT processor. Compared with the other two conventional methods, the proposed bit-reversal method can reduce memory area cost by 53.8 and 46.1%, respectively.

Cache has been introduced into many Graphics processing units (GPUs) to decrease the frequency of data transfer between high-performance computing units and low-speed long-latency external memory. The traditional index mapping scheme designed originally for CPU cache exploits only the spatial locality in address space. The access to graphics data always has region locality on the frame buffer: there are high spatial localities in both X and Y directions. It may generate more conflict misses on some limited cache lines, which eventually results in high cache miss ratio and a performance drop. Traditional CPU cache cannot be used directly in GPU. We propose a new conflict-avoiding GPU cache called XY - type cache with a new index mapping scheme, whose cache line indices are computed from both X and Y coordinates of pixels and the cache index distribution is consistent with the region locality on the frame buffer. Our evaluation results show that the proposed XY -type GPU cache can reduce cache miss ratio by 88% at most via scattering the cache accesses to all lines evenly, and can completely avoid the bad effect caused by frame resolution. Since the cache miss ratio in direct-mapped or 2-way set-associative structure is approximate to or even lower than that in fully-associative structure which is the best case in terms of lowering cache line conflicts, XY -type GPU cache can be designed with lower complexity and lower consumption power.