Modern microprocessors dedicate a large portion of the chip area to the cache. Decreasing the energy consumption of the microprocessor, which is a very important design goal especially for small, battery powered, devices, depends on decreasing the energy consumption of the memory/cache system in the microprocessor. The authors investigate the energy consumption in caches and present a novel cache architecture for reduced energy instruction caches. Our cache architecture consists of the L1 cache, multiple line buffers and a prediction mechanism to predict which line buffer, or L1 cache, to access next. In the proposed technique, the authors use the multiple line buffers as a continuous small filter cache that can catch most of the cache access but they access only a single line buffer, thus reducing the energy consumption of the cache. They used simulation to evaluate the proposed architecture and to compare it with the HotSpot cache, filter cache and single line buffer cache. Simulation results show that the approach is slightly faster than the above mentioned caches, and it consumes considerably less energy than any of these cache architectures.

A resistive switching memory device was fabricated using poly(o-anthranilic acid) (PARA) film. The device has a metal/PARA/metal sandwich-like structure. When the device is biased with voltage beyond a critical value, it suddenly switches from a high resistive state to a low resistive state, with a difference in injection current of more than three orders of magnitude. By controlling the injection current level, it was possible to achieve non-volatile memory behaviour. The devices possess a prolonged retention time of 3×10³ s after switching. The conduction mechanism in the off-state implies that the resistive switching of the device can be explained in terms of filament theory.

Testing for element membership in a Bloom filter requires hashing of a test element (e.g. a string) and multiple lookups in memory. A design of a new two-tier Bloom filter with on-chip hash functions and cache is described. For elements with a heavy-tailed distribution for popularity, membership testing time can be significantly reduced.

A systematic methodology is presented to scale split-gate (SG) flash memory cells in the sub-90 nm regime within the presently known scaling constraints of flash memory. The numerical device simulation results show that the high performance sub-90 nm NOR-type SG cells can be achieved by a suitable channel and source–drain engineering. An asymmetric channel doping profile along with ultra-shallow source–drain junctions was used to achieve the target drain programming voltage (V_sp) for an efficient cell programming while keeping the cell breakdown voltage, BV>V_sp, with tolerable leakage currents. The study shows that with properly optimised technology parameters, 65 nm SG-NOR flash memory can be achieved with an adequate cell read current, a tolerable programmed cell leakage current at the read condition and efficient write and erase times.

While the demand for memory capacity and performance continues to increase, current DDR-2 memory implementations start to encounter limitations. At high data rates of 533 MT/s and above, it becomes increasingly difficult to support greater than two DIMMs on a single DDR channel due to board routing and timing constraints. Supporting different combinations of DDR-2 raw card types on the same platform also complicates the timing and routing due to the possible variations in load. This paper outlines a method of achieving higher data rates of DDR-2 while supporting multiple DIMM configurations on a single platform by utilizing hardware circuitry in the memory controller in connection with software algorithms to adjust the DDR signal timing relationships based on the populated memory configuration. The algorithm also compensate for the effects of ageing over the lifetime of the part. The techniques used in this work are related to DDR-2 but could also be applicable to DDR-3 and future technologies.

While the demand for memory capacity and performance continues to increase, current DDR memory implementations start to encounter limitations. At high data rates of 533MT/s and above, it becomes increasingly difficult to support different combinations of DDR raw card types on the same platform due to the possible variations in load. This paper outlines a method of maximizing the DDR bus performance by utilizing hardware circuitry in the memory controller in connection with software algorithms to adjust the DDR transaction timing relationships based on the populated memory configuration. The algorithm also compensate for the effects of ageing over the lifetime of the part. The techniques used in this work are related to DDR-2 but could also be applicable to DDR-3 and future technologies.

A low-power content addressable memory (CAM)-tagged microprocessor cache using dynamic hierarchical NAND match lines is presented, emphasising the timing impact on overall cache design. Low-capacitive clock loading and lower NAND CAM match line activity factor provide a total cache tag power dissipation savings of up to 64% over a conventional design with NOR match lines. The circuit design, operation and physical layout are described. Results measured on a 0.13-µm low standby power foundry process demonstrate 3.29 fJ/bit/search CAM tag energy at V_DD=0.9 V and nearly 1 GHz operating frequency at V_DD=1.75 V. The NAND match lines allow a completely critical race-free cache memory design, which improves robustness at high-scaled process technology nodes, while maintaining fast single-cycle access times.