http://iet.metastore.ingenta.com
1887

Radiation effects (semiconductor technology)

More general concepts than this:

1-3 of 3 results

Filter by subject:

< Any subject

  • Electrical and electronic engineering [3]
  • Components, electron devices and materials [3]
  • Semiconductor materials and technology [3]
  • Semiconductor technology [3]
  • Radiation effects (semiconductor technology) [3]
  • Circuit theory and circuits [2]
  • Electronic circuits [2]
  • Digital electronics [2]
  • Computer and control engineering [2]
  • Computer hardware [2]
  • See more See less

Filter by content type:

Filter by publication date:

< Any publication date

  • 2015 [3]

Filter by author:

SEU reliability evaluation of 3D ICs
Author(s): Huiyun Li, Xiaobo Hu, Cuiping Shao, Jianbin Zhou, Guoqing Xu
Source: Electronics Letters, Volume 51, Issue 4, February 2015, p. 362 - 364
Type: Article
+ Show details - Hide details

The single-event-upset (SEU) reliability is a concern for three-dimensional (3D) integrated circuits (ICs), mainly due to the carrier mobility change caused by thermo-mechanical stress from through-silicon vias (TSVs) and the shallow trench isolation (STI). A systematic evaluation method is proposed to identify the vulnerability within 3D ICs at design time. The evaluation flow involves the TSV/STI stress-aware mobility variation calculation, sensitive region marking, insertion of excitation signals and then the simulation of the 3D ICs. This method is able to help 3D IC designers to evaluate and enhance the SEU reliability at design time.

Add to favourites
Export citations
Soft error interception latch: double node charge sharing SEU tolerant design
Author(s): K. Katsarou, Y. Tsiatouhas
Source: Electronics Letters, Volume 51, Issue 4, February 2015, p. 330 - 332
Type: Article
+ Show details - Hide details

As technology scales down, soft errors, because of single event upsets (SEUs) that affect multiple nodes (through multiple node charge sharing), become a serious concern in nanometre technology integrated circuits. Existing radiation hardening techniques provide partial or no immunity when more than one node are affected. A new latch topology is presented that guarantees soft error tolerance when a single node or any arbitrary combination of node pairs is affected by an SEU. The proposed scheme exploits a positive feedback loop which consists of C-elements. Simulation results validate the efficiency of the new design over existing soft error hardening techniques such as BISER, FERST and TPDICE.

Add to favourites
Export citations
Efficient error detection in multiple way tables
Author(s): P. Reviriego, J.A. Maestro
Source: Electronics Letters, Volume 51, Issue 1, January 2015, p. 50 - 52
Type: Article
+ Show details - Hide details

Multiple way tables in which items can be placed on several buckets are used in many computing applications. Some examples are cache memories and multiple hash tables structures. In most cases, the items are stored in electronic memories that are prone to soft errors that can corrupt the stored items. To avoid data corruption, memories can be protected with a parity bit or with an error correction code. It is shown that most single bit errors can be detected in multiple way tables without adding a parity bit. This can be done by placing the items in a predetermined order in the multiple ways of the table.

Add to favourites
Export citations
Items per page 20 | 50 | 100
Print this page
This is a required field
Please enter a valid email address