The effect of radiation on digital circuits in particularly complementary metal oxide semiconductor (CMOS) technology has been known since many years. The two most important radiation effects are total ionisation dose and single-event effects (SEEs). The complexity of circuit will increase depends on the number of gate inputs, which degrades the radiation to accelerate the total dose levels. The incremental dose level affects the circuit parameter failure, which affects the functionality of logic design. Many authors focus to reduce radiation effects with avoid function loss, but those extra efforts consume more power. In this study, a low power radiation aware circuit design is proposed. First, the physics-based modelling approach is used for compute radiation response of each component in the circuit. Tri-state inverter embedded non-clocked gating technique is proposed to eliminate unwanted latches and disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals. For simulation purpose, the authors applied their proposed technique in flip–flops and make it as more aware of radiation effects and power consumption. The performance of the proposed circuit design is analysed at 16 nm CMOS predictive technology model in terms of power delay product using HSPICE tool.

On-orbit processors generally require reinforcement due to the harsh space radiation environment. Although the traditional full triple modular redundancy (TMR) method can effectively reinforce circuits, it requires excessive physical footprints and energy consumptions. To address this problem, this Letter proposes a general partial TMR method that can effectively reinforce a circuit. The method is based on the PageRank algorithm for sorting the importance of the triggers in a circuit, and the mean time between failure based on the dual logic cone model is used as the criterion to determine triggers that require redundancy under the partial TMR method. The arithmetic module of an optical image processing platform is tested to verify the effectiveness of the partial TMR method proposed in this Letter.

Area overhead reduction in conventional triple modular redundancy (TMR) by using approximate modules has been proposed in the literature. However, the vulnerability of approximate TMR (ATMR) in the case of a critical input, where faults can lead to errors at the output, is yet to be studied. Here, identifying critical input space through automatic test pattern generation and making it unavailable for the technique of approximating modules of TMR (ATMR) were focused, which involves a prime implicant reduction expansion. The results indicate that the proposed method provides 75–98% fault coverage, which amounts up to 43.8% improvement over that achieved previously. The input vulnerability-aware approach enables a drastic reduction in search space, ranging from 41.5 to 95.5%, for the selection of candidate ATMR modules and no compromise on the area overhead reduction is noticed.

A novel fault tolerant delay cell for ring oscillator (RO) is proposed. As RO is one of the crucial blocks in phased locked loop, delayed locked loo and clock data recovery, it should be tolerated against single event transient (SET) and stuck at faults for harsh environment. Their proposed hybrid fault tolerant topology is combination of triple and quad transistors redundancy, which is applied to the delay cell structure based on the sensitivity role of each transistor. The simulation results with Cadence software show that the proposed fault-tolerant delay cell dissipates 34.34 µW power, while it occupies 127.2 µm² chip area. The proposed topology not only has lower power dissipation in comparison with existing fault tolerant delay cells but also is more reliable against stuck at single and multiple faults and also SETs. By using the proposed reliable delay cell in the RO, the achieved power dissipation and phase noise are about 249 µW and −96 dBc/Hz, respectively, while higher reliability is achieved in comparison with non-redundant RO s.

Single-event transients (SETs) due to heavy-ion (HI) strikes adversely affect the electronic circuits in sub-100 nm regime in radiation environment. Time-to-digital converter (TDC) is an important electronic component in many fields such as space applications and is used for measuring time precisely as a digital value. In this study, the effect of SET due to radiation strike on 45 nm vernier-type TDC with a resolution of 7 ps is analysed using cadence spectre circuit simulator. When HI strikes the delay line of TDC close to the START/STOP pulse transition, it either widens or narrows the time interval to be measured, depending on whether it strikes the top/bottom voltage-controlled delay line (VCDL). Results show that the TDC is sensitive if the SET occurs during the transition of START/STOP pulse. Moreover, the change in the time interval occurs in a regular staircase pattern, if the VCDL is struck at all instants near the pulse transition. These errors lead to erroneous digital output and cause abrupt deviations in the staircase transfer characteristics of TDC. SETs in other constituent components of TDC such as D-flip-flop and priority encoder produces glitches which can be mitigated using existing guard gate technique.

The effect of gamma-ray (γ-ray) irradiation on the material characteristics of nanometre scale films of molybdenum disulphide (MoS₂) has been investigated. 3.2, 4.5, and 5.2 nm thick MoS₂ films (measured by atomic force microscopy) were grown on Si by using a two-step synthesis method (sputtering of Mo, followed by sulphurisation). The samples were subsequently exposed to γ-ray irradiation (dose of 120 MRad). Dramatic chemical changes in the MoS₂ films after irradiation were characterised by micro-Raman spectroscopy, X-ray photoelectron spectroscopy (XPS), and optical microscopy. Micro-Raman spectroscopy showed the disappearance of the E _2g ¹ and A _1g modes after irradiation. XPS revealed that the MoS₂ crystal structure was converted to molybdenum oxide (MoO _x ). It is hypothesised that S vacancies are formed due to the γ-ray irradiation, which subsequently transforms MoS₂ to MoO _x .

In many applications, an incoming value is compared against one or more values stored in registers. To avoid data corruption, the registers are in some cases protected with a single error correction (SEC) code. Therefore, in a traditional implementation, SEC decoding would be done before the comparison. However, previous works have shown that it may be more efficient to compare the SEC encoded values directly using a distance one comparison. This distance one comparison prevents single bit errors from affecting the result of the comparison and is in many cases simpler than an SEC decoding plus a traditional comparison. It is shown that the use of single-error correction double error detection (SEC-DED) encoded registers enables a simplified distance one comparison that can further reduce the cost of implementing error protection for register comparison.

Heavy ion radiation experiments have been done to DC/DC converters with different topological structures for space applications. The test results were analyzed about the function failure of three topological structures caused by single event effects. The relationship between the function failure and the input supply voltage, the output load current and the topological structure of the module were discussed. Based on the analysis of the variation relationship among the source/drain terminal voltage of MOSFETs and the input voltage and the output load, the sensitivity factors associated with the function failure caused by single event effects were discussed. A new analysis on single event function failure of DC/DC converter based on different topologies has been presented, which can be applied to radiation hardened design and space application.

Operation of the 1-transistor, 1-capacitor dynamic random access memory cell that allows for two-bit operation, double the typical storage capacity, is explored. By using a metal-ferroelectric-semiconductor field-effect transistor, a second bit is captured in the ferroelectric layer polarisation resulting from negative and positive polarisation states. As a result, new modes of operation are created giving non-volatile, long-term storage as well as decreased power consumption and radiation hardening. A typical write and read operating cycle is outlined in-depth and used to verify operation indicating four distinct states representing the two bits. The resulting empirical data gives a comprehensive presentation of the read cycle of the memory cell. Methods for determining the polarisation state of the transistor are also explored and used to determine the average value for measured channel resistance using three types of transistors, each having different channel width and length.

The single-event-upset (SEU) reliability is a concern for three-dimensional (3D) integrated circuits (ICs), mainly due to the carrier mobility change caused by thermo-mechanical stress from through-silicon vias (TSVs) and the shallow trench isolation (STI). A systematic evaluation method is proposed to identify the vulnerability within 3D ICs at design time. The evaluation flow involves the TSV/STI stress-aware mobility variation calculation, sensitive region marking, insertion of excitation signals and then the simulation of the 3D ICs. This method is able to help 3D IC designers to evaluate and enhance the SEU reliability at design time.