A fast performance analysis method for NAND flash-based storage devices (NFSDs) is proposed. The method first profiles the operational statistics of an NFSD and then estimates its throughput based on the proposed model. Experimental results show that its accuracy reaches up to 98.7% of the cycle-accurate simulation, while the analysis speedup is more than three orders of magnitude. Also, the generality of the method is shown by applying it to NFSDs with an arbitrary number of channels.

Gate dielectric materials having high dielectric constant, low interface state density and good thermal stability are needed for advanced CMOS applications. In this Letter, the electrical properties of novel multiferroic Bi_0.7Dy_0.3FeO₃ (BDFO) thin films deposited using the pulsed laser deposition technique on p-type (100) silicon substrate are reported. Using high frequency capacitance-voltage (C-V) measurements, the dielectric constant, effective oxide charge density and interface state density were estimated. The results suggest the potential application of multiferroic BDFO films as gate dielectric material for novel memory devices that can be electrically written and magnetically read.

Contemporary FPGA-based reconfigurable systems have been widely used to implement data-dominated applications. In these applications, data transfer and storage consume a large proportion of the system energy. Exploiting data-reuse can introduce significant power savings, but also introduces the extra requirement for on-chip memory. To aid data-reuse design exploration early during the design cycle, the authors present an optimisation approach to achieve a power-optimal design satisfying an on-chip memory constraint in a targeted FPGA-based platform. The data-reuse exploration problem is mathematically formulated and shown to be equivalent to the multiple-choice knapsack problem. The solution to this problem for an application code corresponds to the decision of which array references are to be buffered on-chip and where loading reused data of the array references into on-chip memory happen in the code, in order to minimise power consumption for a fixed on-chip memory size. The authors also present an experimentally verified power model, capable of providing the relative power information between different data-reuse design options of an application, resulting in a fast and efficient design-space exploration. The experimental results demonstrate that the approach enables us to find the most power-efficient design for all the benchmark circuits tested.

Distributed register-file microarchitecture (DRFM), which comprises multiple uniform blocks (called islands), each containing a dedicated register file, functional unit(s) and data-routing logic, has been known as a very attractive architecture for implementing designs with platform-featured on-chip memory or register-file IP blocks. In comparison with the discrete-register-based architecture, DRFM offers an opportunity of reducing the cost of global (inter-island) connections by confining as many of the computations to the inside of the islands as possible. Consequently, for DRFM architecture, two important problems to be solved effectively in high-level synthesis are: (problem 1) scheduling and resource binding for minimising inter-island connections (IICs) and (problem 2) data transfer (i.e. communication) scheduling through the IICs for minimising access conflicts among data transfers. By solving problem 1, the design complexity because of the long interconnect delay is minimised, whereas by solving problem 2, the additional latency required to resolve the register-file access conflicts among the inter-island data transfers is minimised. This work proposes novel solutions to the two problems. Specifically, for problem 1, previous work solves it in two separate steps: (i) scheduling and (ii) then determining the IICs by resource binding to islands. However, in this algorithm called DFRM-int, the authors place primary importance on the cost of interconnections. Consequently, the authors minimise the cost of interconnections first to fully exploit the effects of scheduling on interconnects and then to schedule the operations later. For problem 2, previous work tries to solve the access conflicts by forwarding data directly to the destination island. However, in this algorithm called DFRM-com, the authors devise an efficient technique of exploring an extensive design space of data forwarding indirectly as well as directly to find a near-optimal solution. By applying this proposed synthesis approach DFRM-int+DFRM-com, the authors are able to further reduce the IICs by 17.9%, compared with that by the conventional DRFM approach, even completely eliminating register-file access conflicts without any increase of latency.

Due to the DRAM used in the internal memory of ADSP-TS201 produced by ADI, it is not optimized for random access in the conventional FFT algorithm using standard structure. SingLeton structure is used to ensure that the reads in each stage are sequential. Program flow of this algorithm is introduced, and efficient implementation is provided by using appropriate assembly instructions and well designed software pipeline. Test results shows that the performance of FFT on TS201 is greatly improved, and it can be widely used in radar signal processing. (4 pages)

Proposed is a true random number generator (TRNG) based on collision between DRAM accesses and refresh operations. The generator repeatedly executes a short code and reads a part of time counter register after each execution without an explicit post-processing. The simplicity allows the generation of true random numbers with a reasonable efficiency on commodity desktop computers without special devices and opens the possibility for simple TRNG on devices that use DRAM. Although very simple, the quality of the bit sequence is surprisingly good, as demonstrated by test results using NIST test suite.