Vertical cell transistor is necessary to drastically reduce the chip size of the dynamic random access memory. This structure has a great advantage in terms of shrinkage, but it also has the disadvantage of increasing the OFF-state current by causing floating body effect (FBE). For the first time, it is demonstrated that a stretched tunnelling diode, which consists of a p⁺ layer next to the n⁺ active layer in the buried body, leads to a drastically suppressed FBE. The OFF-state current is sharply reduced by about seven orders compared with a conventional structure. Furthermore, the decrease in the OFF-state current is at minimum when the length of the stretched p ⁺ region is approximately half the channel length (L _p/L=1/2).

With the increase in processing cores performance have increased, but energy consumption and memory access latency have become a crucial factor in determining system performance. In tiled chip multiprocessor, tiles are interconnected using a network and different application runs in different tiles. Non-uniform load distribution of applications results in varying L1 cache usage pattern. Application with larger memory footprint uses most of its L1 cache. Prefetching on top of such application may cause cache pollution by evicting useful demand blocks from the cache. This generates further cache misses which increases the network traffic. Therefore, an inefficient prefetch block placement strategy may result in generating more traffic that may increase congestion and power consumption in the network. This also dampens the packet movement rate which increases miss penalty at the cores thereby affecting Average Memory Access Time (AMAT). The authors propose an energy-efficient caching strategy for prefetch blocks, ECAP. It uses the less used cache set of nearby tiles running light applications as virtual cache memories for the tiles running high applications to place the prefetch blocks. ECAP reduces AMAT, router and link power in NoC by 23.54%, 14.42%, and 27%, respectively as compared to the conventional prefetch placement technique.

Using conventional memory technologies, for example, static random access memory (RAM) (SRAM), dynamic RAM (DRAM) and flash memory, it is difficult to fulfill the market requirements for higher density and lower power dissipation [1]. Therefore, semiconductor organizations are thinking that it is difficult to supply the expanding market interest for the higher density and lower power nonvolatile memories [2]. The recent invention of memristor device has given hope to semiconductor organizations by offering a less demanding approach to expand the density by utilizing the current fabrication technology [3]. This is conceivable on the grounds that memristor devices just require two terminals to work, which utilize less wafer space, reduce the complexity of circuit interconnections and encourage highdensity integration when used as a part of crossbar structures [4-7]. Besides all these features of memristor, it also has some additional characteristics like low power and non-volatility [8]. But the main limitation of the memristor-based memory cell is its slow write time access [9]. Transmission gate is capable of providing rail-to-rail swing and can easily pass both logic “0” and logic “1” [10]. These advantages help to overcome the problem of slow write time access of memristor. The objective of this chapter is to understand what a memristor is and how can a memristor be modeled for its current-voltage (I-V) characteristics. Further, this chapter deals with the concepts of transmission gates, then using the designed memristor and transmission gates, a DRAM cell was designed. The designed memory cell was simulated using HSPICE tool. The result shows that the memristor-based DRAM cell can replace the conventional memory cell in future to achieve higher density and lower power dissipation.

Phase change memory (PCM) functions by thermally induced phase change of chalcogenide material, typically from disordered highly resistive amorphous phase with short range atomic order and low free electron density, to a low resistance crystalline phase with long range atomic order and high free electron density, or vice versa [1,2]. PCM is one of the potential emerging nonvolatile memory (NVM) technologies to replace flash memory and be the technology for storage class memory due to its desirable properties such as short access time, long data retention, high endurance, scalability, CMOS compatibility and multibit storage [3-8]. Hence it is time to have an accurate electrical model of the PCM in order to realise a straightforward and timely implementation of PCM in an integrated circuit. This chapter presents the electrical circuit model of multibit PCM cell that accurately simulates the temperature profile, the crystalline fraction and the resistance of the cell as a function of the programming pulse. Also, the precise modelling of the drift phenomenon of resistance and threshold voltage at the amorphous phase is presented. The presented model's I-V characteristics are correlated with experimental data to demonstrate the validity of the developed PCM model. Next this chapter presents the analysis of PCM cells on a nanocrossbar as a memory system. The effect of connecting wires resistance in the performance of the PCM array structure, the amount of energy lost across each PCM cell and programmed state of the PCM cell is also discussed. It has been shown that the energy consumed in connecting wires decreases the power supplied to PCM cells thus resulting in higher programmed low resistive state (Rcrystalline). Additionally, methods to mitigate the programmedRcrystalline reliability issue are discussed in detail. Finally, the chapter concludes with the discussion on PCM-based memory application in implementing a logic function using the look-up-table (LUT), that is, PCM-based LUTs.

In modern SOC design SRAM has become an integral part owing to its capability to form a bridge and overcome the speed mismatch problem between the high speed processor and the low speed data storage devices. Because of the read and write operation of SRAM cell having conflicting transistor sizing requirement, it is very difficult to maintain the transistor size to satisfy both the needs. The destructive nature of read operation enforces a serious thought about SRAM cell data stability. Transistor sizing and cell stability already being a critical problem becomes even more critical when we consider the process and temperature variation. Thus the SRAM should be designed with keeping the process and temperature variation in mind. The random fluctuation in device parameters such as transistor width, length, oxide thickness, oxide capacitance and doping concentration leads to variation in the threshold voltage and other transistor characteristics. The change in these transistor characteristics alters the SRAM cell performance. Hence this should also be taken care of to ensure the cell performance to be in the desired range even in presence of random fluctuation during fabrication process. The various performance measure such as SNM, write SNM, speed and power consumption must be tested under worst process corner as well over a wide temperature range to ensure that they lie in the acceptable range during worst operating condition. Also these parameters must be tested using Monte Carlo simulation to ensure a robust operation in presence of random fluctuation during fabrication process.

Multicore processors are widely used in today's real-time embedded systems to satisfy the performance and predictability requirements as well as reduce cost. A vast majority of multicore embedded systems are running several tasks with mixed-criticality, in which the non-functional requirements of the tasks are different or even conflicting. A major challenge in mixed-criticality systems is to maximise the efficiency of shared resources while satisfying the criticality requirements. Shared memory is a key component that should be well managed and memory controller plays the main role in this case. Several memory controllers have been introduced in the literature for multicore processors. In this article, the authors performed a deep investigation on three state-of-the-art memory controllers using gem5 full-system simulator and Xilinx ISE Design Suite, and compared them in terms of predictability and performance. Then, the authors proposed a memory controller that provides the same predictability as the most predictable existing controller while improving the performance by 12.3%.

This chapter presents a frame memory compression method used in video coding. Frame memory compression compresses the data to be stored in the frame memory in order to reduce the external bandwidth and the related power consumption, as shown in Figure 7.1. When the pixels of a motion-compensated frame have to be written into external DRAM, the frame memory compression engine compresses those pixels. During motion estimation (ME), the frame memory compression engine decompresses the compressed pixels of previous frames and passes them to the video codec. As shown in Figure 7.2, most of the frame memory compression algorithms are composed of three stages: prediction, entropy coding and memory organization [1], which are respectively introduced in Sections 7.1, 7.2 and 7.3.

Increasing demands to process large amounts of data in real time leads to an increase in the many-core microprocessors, which is posing a grand challenge for an effective and management of available resources. As communication power occupies a significant portion of power consumption when processing such big data, there is an emerging need to devise a methodology to reduce the communication power without sacrificing the performance. To address this issue, we introduce a cognitive I/O designed toward 3D-integrated many-core microprocessors that performs adaptive tuning of the voltage-swing levels depending on the achieved performance and power consumption. We embed this cognitive I/O in a many-core microprocessor with DRAM memory partitioning to perform energy saving for application such as fingerprint matching and face recognition.

This study proposes a single bit-line and disturbance-free static random-access memory (SRAM) cell for ultra-low voltage applications. SRAM cell with read-decoupled and cross-point structure addresses both the read-disturb and half-select stability issues; nevertheless, the write-ability is degraded due to the stacked pass transistors. In this study, the authors propose a single-ended 8T bit-cell and dual word-line control technique that can simultaneously improve the read stability, half-select stability, and write-ability without additional peripheral circuits, which is advantageous for bit-interleaved ultra-low voltage operations. A 4 kb test chip was implemented in a 90 nm complementary metal–oxide–semiconductor process to verify the proposed design. Silicon measurements indicate that the proposed design can operate at a voltage as low as 360 mV with 2.68 μW power consumption.

In high-density three-dimensional (3D) memory technology, a stacking method is used to create memory devices and access devices at the intersections of bit lines and word lines. For this application, access devices should have a high on/off ratio, high current density for writing cycles, and high endurance. Consequently, an arsenic–tellurium–germanium–silicon nitride compound (AsTeGeSiN) threshold switching device with a high current density of 10⁴ A/cm² above the threshold voltage (V _th) is reported as a good candidate for use in access devices. In addition, scaling down of access devices as well as memory devices is essential for high-density 3D memories. However, in AsTeGeSiN threshold switching devices, fast degradation by pulse cycling in smaller devices is observed. To find the main cause of fast degradation by pulse cycling in smaller devices, the low-frequency noise properties are examined. The rapid increase in the trap density (N _T) in small devices is the main cause of fast degradation by pulse cycling in AsTeGeSiN devices. On the basis of this evaluation, the author examines the effect of annealing temperature and annealing time on the pulse endurance in smaller devices. Using an annealing temperature of ∼600°C improves the cycling endurance of smaller devices.

NAND flash memories, due to their several advantageous characteristics, have recently dominated the data storage industry and its global market. Currently, multi-level cell memories, in which each cell can store more than one bit of data resulting in higher data storage capacities, have gained a considerable amount of research interest. However, this comes at the cost of several limitations and increased performance degradation. Various studies have shown that among several error sources in multi-level cell memories, inter-cell interference is the most significant one. Therefore, to mitigate the devastating effect of the interference, simple, feasible, and yet efficient equalisation techniques become essential for achieving desired data reliability. In this study, first, a thorough analysis on deriving the distribution of the interference-free and interference-affected data is carried out. Then, novel low-complexity equalisation methods are proposed, and their beneficial complexity-performance trade-offs compared with the existing techniques are illustrated. Finally, simulation results are presented to show that the proposed algorithms considerably improve the error performance, while maintaining the low-complexity constraints.

This work investigates the delay performance of junctionless silicon nanotube (JLSiNT) field-effect transistor (FET) based 6T SRAM cell. The study demonstrates that the delay performance of symmetric drain/source DS-JLSiNT FET (inner gate covers drain, channel, and source regions) based 6T SRAM gets improved when the inner gate of nanotube covers only either drain and channel regions (D-JLSiNT FET) or source and channel regions (S-JLSiNT FET) because of improved I _on/C _gg. The improvement in read (write) access time is ∼22% (17%) and ∼9% (20%) when DS-JLSiNT FET is replaced by D-JLSiNT FET and S-JLSiNT FET, respectively, in DS-JLSiNT FET based 6T SRAM. Furthermore, due to partial covering of inner gate, the gate electrostatic integrity is reduced which decreases the ratio of on-current to off-current (I _on/I _off) resulting in degraded static noise margin (SNM). However, the deterioration in write SNM, hold SNM, and read SNM are almost minimal (∼0.3, 0.9, and 2%, respectively) for S-JLSiNT FET based SRAM as compared to DS-JLSiNT FET based SRAM. However, the deterioration in SNMs is aggravated for D-JLSiNT FET based SRAM as compared to DS-JLSiNT FET based SRAM. Thus, S-JLSiNT FET is the best configuration for designing of JLSiNT FET based 6T SRAM cell.

Generalised concatenated (GC) codes are well suited for error correction in flash memories for high-reliability data storage. The GC codes are constructed from inner extended binary Bose–Chaudhuri–Hocquenghem (BCH) codes and outer Reed–Solomon codes. The extended BCH codes enable high-rate GC codes and low-complexity soft input decoding. This work proposes a decoder architecture for high-rate GC codes. For such codes, outer error and erasure decoding are mandatory. A pipelined decoder architecture is proposed that achieves a high data throughput with hard input decoding. In addition, a low-complexity soft input decoder is proposed. This soft decoding approach combines a bit-flipping strategy with algebraic decoding. The decoder components for the hard input decoding can be utilised which reduces the overhead for the soft input decoding. Nevertheless, the soft input decoding achieves a significant coding gain compared with hard input decoding.

Fast search block matching algorithm (BMA)-based video coding provides reasonable good quality video with minute cost of computation. In fast BMA, clock cycles required to read pixel data are quite more compared with matching operation due to erratic location of candidate macroblocks (CMBs). With aim of reduction in number of clock cycles, parallel memory system is used in this study, which can accelerate reading of CMBs and speedup motion vector (MV) computation. Novel concept of register array is introduced to organise CMBs, which expedite computation hungry search process. Owing to shape of register array, lesser space is needed to store CMBs and architecture addresses wide range of search patterns. The proposed sum of absolute difference processor with parallel memory system computes MV of 1 macroblock in 28 clock cycles in average case. Compared to single memory system, it saves 68% and 80% clock cycles in CMB access of initial search and intermediate search process, respectively. Hardware architecture is tested with Xilinx Virtex5 field programmable gate array. The proposed fixed 8×8 macroblock size architecture processes 354 high definition (HD) (1080p) frames per second (fps) and configurable architecture processes 201 HD fps which is more than adequate for real-time encoding.

An open-loop per-pin skew compensation with lock fault detection is presented. The proposed circuit employs an open-loop reference selector, a two-stage open-loop delay lock method which is separated by a coarse and fine lock for fast lock-in time, and a fault lock detecting scheme to prevent lock fault by dead zone of samplers. A unidirectional scan method ahead the fine lock stage to minimise pin-to-pin skew errors after calibration is also applied. The circuit was fabricated with 55 nm CMOS technology with a 1 V supply voltage and an area of 0.0036 mm² for one de-skewing module. The measured result shows that the skew error at 1 GHz operation was reduced to <6 ps after skew calibration when the skew between input/output (IO) pins was 230 ps, and the lock-in time was 11 clock cycles.

Solid state drives (SSDs) achieve a significantly better performance than hard disks by internally implementing channel level, chip level, and die level parallelism. However, the plane level parallelism has not been sufficiently exploited, because of the constraint that the target pages of the planes must be in the same location. To overcome this constraint, a policy that enforces the multi-plane operation by matching the position of the target pages while wasting clean pages is proposed. However, this policy excessively increases the number of block erasures, which leads to reducing the stability and lifetime of the SSD. To solve this problem, this Letter proposes a policy that determines whether to perform the multi-plane operation considering the number of wasted clean pages. The performance evaluation using representative server workloads shows that the proposed policy improves an average performance by up to 28.82% over the policy that does not perform the multi-plane operation, without significantly increasing the number of block erasures.

This Letter proposes an on-chip data strobe transmission circuit for dynamic random access memory (DRAM). The on-chip differential repeaters with cross-coupled latches are adopted to prevent the sampling margin reduction. A node monitoring circuit has been proposed to prevent short-circuit currents of the on-chip differential repeaters and cross-coupled latches caused by high impedance inputs. When compared with the conventional differential signalling, the proposed circuit can save the short-circuit current of 6.2 mA per a single write operation. The chip has been fabricated in 350 nm CMOS technology and the active chip area is 0.189 mm².

Among resistive random access memory (RRAM) architectures, one transistor one memristor (1T1R) crossbar is the most fledged one. For 1T1R crossbar, a logic operation-based Design for Testability and parallel test algorithm, which is an improvement of March C*-1T1R test algorithm, are proposed. The pass-fail fault dictionary of the proposed test algorithm is analysed. Analytical results show that the proposed test algorithm can detect all the modelled faults caused by the parametric variation of memristors and traditional RAM. Compared with March MOM, March C* and March C*-1T1R, the test time of the proposed test algorithm is reduced with a little area overhead for a large size crossbar.

A building block for computing in memory systems is introduced. Based on the previously introduced racetrack memory proposed by IBM, a racetrack memory is used not only to store data but also to perform bitwise majority-based computations by coupling the memory with inputs provided by controllable magnets. This solution is defined as racetrack logic. Micromagnetic simulations are used to confirm that the proposed solution is technically viable.

High-density and high-speed charge-trapping AND flash memory array is fabricated for the first time. A reliability of 10⁴ endurance cycles and uniform program/erase characteristics along with a threshold voltage window >3 V is obtained. The AND array has several advantages, such as high read current drivability regardless of the number of word-lines, immunity to back-pattern dependency, and fast bit-sensing speed based on a parallel connected cell array structure, which are highly appropriate for three-dimensional (3D) stacking. Finally, a novel 3D stacked vertical-AND array is proposed to surpass the limitations of the conventional 3D NAND flash memories.

Spin-torque transfer RAM (STT-RAM) is a promising candidate to replace SRAM for larger Last level cache (LLC). However, it has long write latency and high write energy which diminish the benefit of adopting STT-RAM caches. A common observation for LLC is that a large number of cache blocks have never been referenced again before they are evicted. The write operations for these blocks, which we call dead writes, can be eliminated without incurring subsequent cache misses. To address this issue, a quantitative scheme called Feedback learning based dead write termination (FLDWT) is proposed to improve energy efficiency and performance of STT-RAM based LLC. FLDWT dynamically learns the block access behavior by using data reuse distance and data access frequency, and then classifies the blocks into dead blocks and live blocks. FLDWT terminates dead write block requests and improves the estimation accuracy via feedback information. Compared with STT-RAM baseline in the lastlevel caches, experimental results show that our scheme achieves energy reduction by 44.6% and performance improvement by 12% on average with negligible overhead.

Three kinds of parameters are considered to speed up the read operation of phase change memory: bit line parasitic parameters, read transmission gate parasitic parameters and current mirror parasitic parameters. A set reference cell and a reset reference cell are used in the reference circuit. Simulated in 130 nm process, the read access time of 1-Mb phase change memory (PCM) is 6.7 ns. In Monte Carlo simulations, the worst read access time is 13.8 ns compared to conventional 85 ns.

Recently, multi-level cell (MLC) spin-transfer torque random access memories (STT-RAMs) are attracting great attentions as an alternative to static or dynamic random access memories. They have the benefits of capacity, but the penalties of performance, and power consumption caused by a complicated two- or three-phase access. An MLC STT-RAM controller that eliminates the MLC STT-RAM penalties for multimedia applications is proposed. The key ideas are frame-level data-to-memory mapping and frame-type aware frame assignment techniques that make a two- or three-phase access no longer required. Experimental results show that the proposed MLC STT-RAM controller achieves 56.1% higher memory performance, and 4.2% lower memory power consumption than the conventional controller for industrial multimedia applications.

Soft errors in semiconductor memories occur due to charged particle strikes on sensitive nodes. Technology and voltage scaling increased dramatically the susceptibility of static random access memories (SRAMs) to soft errors. In this study, the authors present AS8-SRAM, a new asymmetric memory cell that enhances the soft error resilience of SRAMs by increasing the cells critical charge. They run Simulation Program with Integrated Circuit Emphasissimulations and system level experiments to validate the AS8-SRAM cell characteristics at circuit level and evaluate the energy and reliability effectiveness of an AS8-SRAM-based cache memory. The authors’ results show that AS8-SRAM presents up to 58 times less failures in time compared to six-transistor SRAM. Moreover, based on embedded benchmarks experimentations, AS8-SRAM achieves up to 22% reduction in energy-delay product without any considerable loss in performance.

A fuzzy static RAM (SRAM) is proposed, which is applicable in fuzzy logic and many multiple-valued logic (MVL) applications. The new structure is basically an extension to the binary SRAM cell. Two cross-coupled voltage mirror circuits are used to be able to hold an arbitrary voltage value. The proposed design forms a robust and reliable structure, which is capable of operating with more than 95% accuracy in spite of imperfect fabrication of carbon nanotube FETs. Another exceptional advantage is its ultra-low-power consumption in MVL environments. It consumes 38.7 and 99% less static power compared with the SRAMs with regular ternary and quaternary components, respectively.

This study introduces an inexact, but ultra-low power, computing architecture devoted to the embedded analysis of bio-signals. The platform operates at extremely low voltage supply levels to minimise energy consumption. In this scenario, the reliability of static RAM (SRAM) memories cannot be guaranteed when using conventional 6-transistor implementations. While error correction codes and dedicated SRAM implementations can ensure correct operations in this near-threshold regime, they incur in significant area and energy overheads, and should therefore be employed judiciously. Herein, the authors propose a novel scheme to design inexact computing architectures that selectively protects memory regions based on their significance, i.e. their impact on the end-to-end quality of service, as dictated by the bio-signal application characteristics. The authors illustrate their scheme on an industrial benchmark application performing the power spectrum analysis of electrocardiograms. Experimental evidence showcases that a significance-based memory protection approach leads to a small degradation in the output quality with respect to an exact implementation, while resulting in substantial energy gains, both in the memory and the processing subsystem.

Harmonic resistive multipliers that exploit the unique current–voltage (I–V) characteristics of Ag/Ge–(Sb)–Te/Pt resistive-switching devices are demonstrated. For a Ge₁₇Sb₂₉Te₅₄-based device, an antisymmetric non-linear I–V curve with a hump-like structure at ±0.4 V is obtained, whereas for a Ge₅₁Te₄₉-based device, an asymmetric non-linear I–V curve with SET switching at +0.4 V and RESET switching at –0.1 V is observed. The Ge₁₇Sb₂₉Te₅₄-based device performs third harmonic multiplication for a 160 MHz input at 0 dBm, and sixth harmonic multiplication at 5 dBm under unbiased conditions without any matching circuit. For the latter device, biasing at a voltage of ±0.4 V leads to fifth harmonic multiplication, which is absent for a 0 dBm input under unbiased conditions. No harmonic multiplication is observed for an unbiased Ge₅₁Te₄₉-based device due to its high resistance, but biasing at the switching voltage of 0.4 V leads to fourth harmonic multiplication for a 0 dBm input. The unique non-linear characteristics of these devices suggest their potential for radio frequency applications.

This Letter presents a self-controlled physical unclonable function (PUF) circuit and its application in encrypting on-chip memories of IC bank cards. The PUF circuit is based on cross-coupled NAND gates. Voting and Hamming code address the stability of its outputs. The Monte Carlo simulation and field-programmable gate array board are used for verification. The Voting method improves the error rate 79%. The Hamming codes and convertor can correct every error bits of PUF outputs. The PUF outputs, data address and time-stamp are encrypted by SM4 (Chinese block cipher algorithm standard) to generate KEY. The data does XOR with the KEY.

To simplify power-gating requirements in ultra-low-power architectures, design strategies for low-power non-volatile flip-flops (F/Fs) are sought, for which the utilisation of spintronic devices offers a promising option. A D F/F that utilises a five-terminal spintronic device for non-volatile state holding in an intrinsically self-complementing fashion is introduced. This self-complementing device can be exploited to reduce overhead interfacing circuitry in order to realise a compact ten transistors with one spintronic device D F/F with instant store and restore functionality, while consuming <9 µW of power.

A ferroelectric-gated graphene field-effect transistor was fabricated by consecutively stacking two distinct graphene–ferroelectric hybrid ribbons at right angles. Two graphene layers play different roles. One graphene layer acts as a gate electrode and the other graphene layer acts as a channel between two electrodes, source and drain. Electric gating at the gate graphene modulates the resistance of the channel graphene. By means of ferroelectric polarisation, bistable resistance states of the channel graphene could be recorded, and the retention time of bistability was estimated to be 460 days by extrapolating of two resistance values in time–resistance relationships. Furthermore, the underlying concept to fabricate bistable memory device was extended to the methodology to realise a logic-gate device by stacking three distinct graphene–ferroelectric hybrid ribbons.

Novel two-transistor embedded memory – floating body gate cell – is implemented on planar SOI CMOS technology without adding extra masks. Since channel current is designed for memory cell write operations, this cell demonstrates ultra-fast write speed which is comparable with static RAM cell. The decoupled write and read structure ensures small operation power consumption and avoid false read. The low operation voltages of this cell lead to the excellent endurance performance. In addition, retention time is greatly enhanced due to the gate-to-drain underlap design.

An inverted bit-line sense amplifier (BLSA) equipped with offset compensation capability for low-power DRAM applications is proposed. The sequential operation of the inverted BLSA allows us to eliminate the edge dummy array in an open bit-line structure resulting in 1.7% less total chip area despite of 10% area penalty of the proposed BLSA occupied by extra switches. For 8-Gb DRAM in 20-nm class technology, the read failure induced by Vth variability is completely removed due to the offset cancellation. The proposed BLSA maintains the gradual increase of the sensing delay when decreasing the power supply down to 0.6 V, while intrinsic read fail prevails below 0.9 V with the conventional one.

Six-transistor static random-access memory (6T SRAM) cell is the fundamental building block of memory cache in modern microprocessors. Each bit of data is stored in an individual 6T SRAM cell in the memory subsystem. Read data stability and write ability of 6T SRAM cells are degraded with the scaling of CMOS technology. Conventional circuit techniques for achieving wider voltage margins during read and write operations cause significantly larger silicon area and increased power consumption. Several alternative FinFET memory design techniques are presented in this chapter for achieving stronger data stability during read operations and wider voltage margin during write operations without causing area and power consumption overheads in the memory subsystems of microprocessors.

Operation of the 1-transistor, 1-capacitor dynamic random access memory cell that allows for two-bit operation, double the typical storage capacity, is explored. By using a metal-ferroelectric-semiconductor field-effect transistor, a second bit is captured in the ferroelectric layer polarisation resulting from negative and positive polarisation states. As a result, new modes of operation are created giving non-volatile, long-term storage as well as decreased power consumption and radiation hardening. A typical write and read operating cycle is outlined in-depth and used to verify operation indicating four distinct states representing the two bits. The resulting empirical data gives a comprehensive presentation of the read cycle of the memory cell. Methods for determining the polarisation state of the transistor are also explored and used to determine the average value for measured channel resistance using three types of transistors, each having different channel width and length.

Single-error correction, double-error detection (SEC–DED) codes are a type of error-correction codes widely used in electronics to protect memory devices from data corruption. Odd-weight-column SEC–DED codes are a type of these codes where the parity-check matrix is built with every column including an odd number of ones. With this approach, double errors have an even-weight syndrome and can be differentiated from single errors and, consequently, easily detected. There are applications, such as avionics or space, where a multiple error usually affects adjacent cells. Adapting SEC–DED codes to protect against triple-adjacent errors is interesting in these applications. A modification to existing odd-weight-column SEC–DED codes to add triple-adjacent error detection (TAED), creating SEC–DED–TAED codes, is presented. The implementation of the additional triple-adjacent detection logic for these codes can be performed with limited performance and area overhead.

To increase storage capacity and I/O bandwidth, modern solid-state drives embed multiple NAND packages that consist of one or multiple dies in a parallel architecture. Each die can process NAND read/write/erase operations independently. A dynamic die binding method for write requests that is intended to exploit this parallel processing capability is proposed. This scheme stripes data to idle dies first, and unlike existing dynamic binding schemes, when idle dies are lacking it selects dies with the lowest accumulated write loads, thereby achieving wear levelling by ensuring long-term write load balancing. Thus, it can prevent situations in which some dies are worn out more quickly than others. A performance evaluation demonstrates that our approach offers slightly better performance compared with an existing dynamic binding scheme and completely resolves the problem of imbalanced write loads.

With the advent of multiple cores on a single chip, it is common for the systems to have multi-level caches. Multiple levels of cache reduce the pressure on the memory bandwidth by allowing applications to store their frequently accessed data in them. The levels of cache nearer to the core filter the locality in the application access, which can result in high miss rates at farther levels. This piece of study revolves around one question: are all levels of cache needed by all applications during all phases of their execution? The study observes the effect of 2-level and 3-level cache hierarchies on the performance of different applications. On the basis of this study, this study proposes an application aware cache management policy called ‘SkipCache’, which allows an application to choose a 2-level or 3-level cache hierarchy during run-time. SkipCache dynamically tracks the applications at shared last-level cache (LLC) to identify the applications that do not obtain advantage by using the LLC. Such applications can completely skip the LLC so that other co-scheduled cache friendly applications can efficiently use it. Evaluation of SkipCache in a 4-core chip multi-processor with multi-programmed workloads shows significant performance improvement. SkipCache is orthogonal to other cache management techniques and can be used along with other optimisation techniques to improve the system performance.

Quantum dot gate field-effect transistor (QDGFET) generates three states in their transfer characteristics. A successful model can explain the generation of third state in the transfer characteristics of the QDGFET. The innovative circuit design using QDGFET can be used to design different ternary logic. This Letter discusses the design of ternary logic static random access memory using QDGFET.

In this paper, a new voltage mirror circuit by using carbon nanotubes (CNTs) technology is presented. This circuit is specifically proposed for the application of duplicating multiple-valued and fuzzy dynamic random access memories. The given structure prevents any voltage drop for the capacitor inside the memory cell. As a result, any fanout circuit can be driven. The new structure can be utilised for different multiple-valued logic systems without a change. The unique characteristics of carbon nanotube field effect transistor (CNFET) technology are exploited in this paper to meet the desired design goals. It demonstrates the potentials of CNFET technology in a realistic very large-scale integration application. The proposed design is highly tolerant to D _CNT variation and it is also immune to misaligned CNTs. Simulation results demonstrate that it provides sufficient driving capability with reasonable accuracy.

An efficient replica bitline (RBL) technique for reducing the variation of sense amplifier enable (SAE) timing is proposed. Both RBLs and four-fold replica cells compared with the conventional RBL technique are utilised to favour the desired operations. Simulation results show that the standard deviation of SAE can be suppressed by 44.25% and the cycle time is also reduced by ∼30% at a 0.8 V supply voltage in TSMC 65 nm technology. Additionally, the area of the proposed scheme is nearly the same as that of the conventional RBL scheme.

A low-cost memory data scheduling method based on two N/2-depth single-port memories is proposed for reconfigurable fast Fourier transform (FFT) bit-reversed data reordering tasks. To make single-port memories have the equivalent ability to read and write data simultaneously, two types of read and write address generation methods are proposed. Based on the proposed data scheduling method, the bit-reversal circuits are designed for continuous data reordering tasks. The proposed bit-reversal design is implemented for a maximum 8 k flexible length FFT processor. Compared with the other two conventional methods, the proposed bit-reversal method can reduce memory area cost by 53.8 and 46.1%, respectively.

Cache has been introduced into many Graphics processing units (GPUs) to decrease the frequency of data transfer between high-performance computing units and low-speed long-latency external memory. The traditional index mapping scheme designed originally for CPU cache exploits only the spatial locality in address space. The access to graphics data always has region locality on the frame buffer: there are high spatial localities in both X and Y directions. It may generate more conflict misses on some limited cache lines, which eventually results in high cache miss ratio and a performance drop. Traditional CPU cache cannot be used directly in GPU. We propose a new conflict-avoiding GPU cache called XY - type cache with a new index mapping scheme, whose cache line indices are computed from both X and Y coordinates of pixels and the cache index distribution is consistent with the region locality on the frame buffer. Our evaluation results show that the proposed XY -type GPU cache can reduce cache miss ratio by 88% at most via scattering the cache accesses to all lines evenly, and can completely avoid the bad effect caused by frame resolution. Since the cache miss ratio in direct-mapped or 2-way set-associative structure is approximate to or even lower than that in fully-associative structure which is the best case in terms of lowering cache line conflicts, XY -type GPU cache can be designed with lower complexity and lower consumption power.

This study documents the speeds of various SRAM buffer memories that are possible in a contemporary fast SiGe heterojunction bipolar transistor (HBT) BiCMOS process. An SRAM in a 0.13 µm HBT BiCMOS technology using current mode logic (CML)-style circuits serves as a basis for the discussion. This basic SRAM design features a CML decoder, CML word line driver, bipolar sense amplifier for achieving high speed and CMOS 6T memory cells for high density. The BiCMOS technology is especially useful for realising ultra-high-speed SRAMs for low level cache memory in high-clock rate computer systems, but when reorganised can also be utilised in analogue-to-digital converter (ADC) systems to store digitalised data. Speed and power tradeoffs can be made using different bias strategies, CML logic levels and different generations of SiGe HBTs. A demonstrated 128 kb SRAM macro consumes 2.7 W at 4 GHz using a −3.4 and −1.5 V supply voltage for the bipolar and CMOS circuits, respectively, and has dimensions of 3.5 mm × 3.6 mm by using IBM 8HP SiGe technology, which provides an HBT with a f _T of 210 GHz. This macro can be integrated into large scale, ultra-wide bus SRAMs using heterogeneous silicon and 3D technology. Simulation indicates that with the next generation of SiGe HBTs, this SRAM macro can operate at 5 GHz, while consuming the same amount of power or alternatively consume 0.73 W, which is 73% less power consumption compared to 8HP, while operating with the same frequency of 4 GHz. Reorganising the memory for a 4 way-interleaved ADC, it can accept data written at 9.5 GS/s for 8HP designs, and 11.9 GS/s for 8XP designs.

Magnetic random access memory based on magnetic tunnel junctions (MTJs) is among the most attractive technologies of emerging non-volatile memories. However, the integration of spin-based devices in integrated circuits is still hindered by a lack of established standard electrical simulator models. Many of such models have been proposed during the past decade which can be classified into two categories: the first ones are based on the physical Landau-Lifshitz-Gilbert (LLG) equation describing real-time MTJ magnetic switching dynamics; the second one uses analytical expressions for switching thresholds derived from the LLG equation. The aim of this reported work was to investigate for the first time the capability of each strategy to fulfil the need of industrial standard electrical simulation tools and pave the path towards a standard industrial model. Multi-simulator compatibility, efficient runtime, accuracy and reliability are the three main assets of a device model. It is shown that using the Cadence^® tools suite with the Spectre^® simulator, the LLG modelling strategy overcomes the analytical approach in terms of accuracy and speed with a 7× faster runtime. Both models require nearly the same hardware memory resources.

In this paper, the authors propose a novel static random access memory (SRAM) that employs the adiabatic logic principle. To reduce energy dissipation, the proposed adiabatic SRAM is driven by two trapezoidal-wave pulses. The cell structure of the proposed SRAM has two high-value resistors based on a p-type metal-oxide semiconductor transistor, a cross-coupled n-type metal-oxide semiconductor (NMOS) pair and an NMOS switch to reduce the short-circuit current. The inclusion of a transmission-gate controlled by a write word line signal allows the proposed circuit to operate as an adiabatic SRAM during data writing. Simulation results show that the energy dissipation of the proposed SRAM is lower than that of a conventional adiabatic SRAM.

This study presents an efficient method for converting a normalised binary number x (1 ≤ x < 2) into a binary logarithm. The algorithm requires less memory and fewer arithmetic components to achieve 23 bits of fractional precision than other algorithms using uniform and non-uniform piecewise linear or piecewise polynomial techniques and requires less than 20 kbits of ROM and a maximum of three multipliers. It is easily extensible to higher numeric precision and has been implemented on Xilinx Spartan3 and Spartan6 field programmable gate arrays (FPGA) to show the effect of recent architectural enhancements to the reconfigurable fabric on implementation efficiency. Synthesis results confirm that the algorithm operates at a frequency of 42.3 MHz on a Spartan3 device and 127.8 MHz on a Spartan6 with a latency of two clocks. This increases to 71.4 and 160 MHz, respectively, when the latency is increased to eight clocks. On a Spartan6 XC6SLX16 device, the converter uses just 55 logic slices, three multipliers and 11.3kbits of Block RAM configured as ROM.

This paper presents a highly integrated sinusoid reference generating system based on Microblaze, suitable for precise testing of protective relays. Microblaze, a soft CPU core, was embedded in a FPGA that integrates an ADC interface, a DAC interface, an EEPROM and other peripherals. The prototype and transfer functions of various types of digital filters were designed with reference to the characteristic of the required output signal. Their functional behaviour were implemented in the system on chip using a recursion algorithm. As a critical factor in the digital reference design, a detailed discussion has been performed to introduce the theory of three types of closed-loop control, i.e. amplitude, frequency and phase control. A digital PI control algorithm was implemented in the system to satisfy the control target. The experimental results indicate that the relay evaluation system, using this sinusoid reference, operates correctly. The paper will demonstrate how the performance of the output sine signal improves, as compared with the normal sine reference, especially when outputting low amplitude signals. The research methodology of this reference system and this highly integrated circuit are significant for the optimization of a relay testing system, and provide a theoretical justification and a feasible implementation for a precise relay testing system.

A swap time-aware garbage collection (STGC) policy for the NAND flash-based swap system is proposed, which focuses on reducing the cleaning cost and improving the degree of wear-levelling. STGC calculates the cleaning index value of each block to select a victim block and the normalised value of the elapsed swap time of each valid page within the victim blocks to identify the hot valid page and cold valid page. Trace-driven simulations with a synthetic trace show that the STGC outperforms the existing garbage collection policies.

Design and implementation of a fully table look-up digital pulse-width modulation (DPWM) controller for high-frequency DC–DC buck conversion is presented. The controller comprises a 1 bit analogue comparator, a digital error process unit and a fully table look-up multi-phase DPWM. The interface of analogue-to-digital conversion is performed with the analogue comparator. Moreover, the proposed programmable memory is based on the table look-up multi-phase approach for the functions of the proportional-integral-derivative (PID) compensation, which alleviates the penalty of using large chip-area multipliers. As a result, the approach is very suitable for system-on-a-chip (SOC) implementation. A prototype test chip is realised to validate the mechanism of the proposed architecture.

A design for an integer motion estimator of high-efficiency video coding (HEVC) is presented. HEVC supports the 64 × 64 coding tree unit, the recursive quad-tree coding unit structure and the asymmetric motion-partitioning mode in a high compression ratio. These features require a structure of integer motion estimation that is more complex than that of H.264/AVC. The new structures of a memory read controller and a sum of absolute difference (SAD) summation block are proposed. The new memory read controller reduces the internal memory read time, and the new SAD summation block structure supports the recursive quad-tree coding unit structure and the asymmetric motion-partitioning mode. The proposed design is implemented in Verilog HDL and synthesised using the 65 nm CMOS technology. The gate count is 3.56 M, and the internal static random access memory is about 20 kbyte. The operation frequency is 250 MHz when a 4 K-Ultra high definition (UHD) (3840 × 2160P at 30 Hz) sized video is encoded.