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Design and development of memristor-based RRAM
Author(s): Soumitra Pal, Vivek Gupta, Wing Hung Ki, Aminul Islam
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Type: Article
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A power- and variability-aware non-volatile resistive random access memory (RRAM) cell is presented. Non-volatility is achieved due to the use of a memristor as a memory element, which when integrated with a carbon nanotube field-effect transistor (CNFET) helps achieve tremendous robustness against process variation. The half-select issue, inherent in the 2T2M RRAM cell (state-of-the-art design based on the memristor) have been resolved and its circuit parameters have been compared with those of the proposed cell. Also, the proposed cell has been compared with the standard 6T SRAM (S6T) cell. The proposed cell shows 1.6×/4.08× narrower read delay/write delay variability compared with 2T2M. 5CNFET2M also shows 1.8× narrower read delay variability than that of S6T. Furthermore, the proposed cell shows 6.9× shorter write delay in comparison with the 2T2M RRAM cell. 5CNFET2M consumes 106×/1.34× lower power during hold mode compared with the conventional 6T static random access memory/2T2M RRAM cell. Furthermore, the proposed cell also shows improvement in hold power variability compared with both the cells. All the simulated data, presented here are at the nominal supply voltage of 1 V. These improvements are gained at the expense of slightly longer read time compared with 2T2M/S6T and 31.3× longer write delay compared with S6T.

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Transmission gate-based 9T SRAM cell for variation resilient low power and reliable internet of things applications
Author(s): Soumitra Pal, Vivek Gupta, Wing Hung Ki, Aminul Islam
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Higher variation resilience, lower power consumption, and higher reliability are the three principal design metrics for designing a static random-access memory (SRAM) cell. The most intuitive way to achieve lower power consumption is voltage scaling. However, voltage scaling at nanometre technology nodes leads to degradation in the robustness of the SRAM cell and decreased data stability. It is proved that conventional 6T SRAM fails to maintain its stability in scaled technology, particularly in the deep-subthreshold regime. Furthermore, SRAM cells utilising techniques such as read decoupling, for achieving reliable read operation, tend to increase leakage current resulting in higher hold power, which contributes a major portion to the total power consumption in modern internet of things devices. To cater to the requirements of higher robustness and lower hold power dissipation, a transmission gate-based 9T SRAM is proposed, which achieves these requirements at the cost of slightly higher read and write access time. The simulations are performed utilising a 16-nm complementary metal oxide semiconductor model.

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