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A FPGA ray tracing scheme with memory optimization facility
Author(s): Huang Wei, Wan Wang Gen
Source: IET International Communication Conference on Wireless Mobile and Computing (CCWMC 2011), 2011, p. 329 - 334
Type: ConferencePaper
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This article presents a ray tracing acceleration system realized on FPGA platform. Additionally we make improvement to the memory accessing performance and achieve ideal ratio of performance against resources. Such work will gain ray tracing more applicable regions. The global scheme includes spatial indexing hierarchy module, ray generation module, pre-masking module, packet traversal module, arithmetic module and memory optimization facility which is described specially in this article..

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A spatial hierarchy FPGA implementation with DPR square root partitions
Author(s): Huang Wei, Wan Wang Gen
Source: IET International Communication Conference on Wireless Mobile and Computing (CCWMC 2011), 2011, p. 335 - 340
Type: ConferencePaper
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The customized hardware platform for spatial hierarchy construction with DPR square root partitions is validly obtained. Specialized process structures and storage structures are constructed to ensure the reutilization of presorting results on each level. The objective functions for division evaluation oriented to specific applications are scheduled. DPR partitions are built to meet intensive square root finding requests. After optimizations for algorithm and architecture, such achievement provides the starting points for future development.

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