Tunnel field-effect transistor (TFET) is considered to have superior device performance compared with DG-metal–oxide–semiconductor FET in terms of reduced off-state current and lower subthreshold swing. However, performance of a device solely depends on the accuracy in the fabrication process. This work presents a systematic methodology in small-signal-radio-frequency (RF) and linearity domain to analyse the effect of variation in lateral straggle caused by the variation tilt angle during ion implantation process. From previously published researches, it is intuitively established fact that the accurate evaluation of intrinsic components and estimation of linearity in short channel devices is crucial to access the range of application of the device. In this work, the authors have investigated the RF intrinsic parameter performances of a silicon double gate TFET having variation in lateral straggle from 1 to 5 nm. This study includes the analysis of non-quasi-static RF bias-dependent parameters such as intrinsic capacitances (C _gs, C _gd), gate-to-drain intrinsic resistance (R _gd) and intrinsic time delay (τ). Similarly, the device linearity and reliability are investigated here in terms of higher-order transconductances (g_{m 2} and g_{m 3}), VIP₂, VIP₃, IMD₃, IIP₃ and 1 dB compression point.