This study proposes a novel electrically doped tunnel field effect transistor (ED-TFET), which combines thermionic emission and band to band tunnelling by using an additional metal source (MS) of appropriate work function (WF; 3.9 eV) by forming an ohmic junction between metal and silicon. The ohmic junction is created below the channel region near the source channel junction by depositing of appropriate workfunction metal (lower than silicon) which injects extra electrons through over the barrier along with band to band tunneling (BTBT) in the channel of the device. Therefore, a drastic improvement in the ON state current is observed which is numerically about 107 times greater than conventional ED-TFET. Furthermore, the radiofrequency figures of merit such cut-off frequency, gain band width product, and maximum oscillating frequency are enhanced by ∼, 20 and 1000 times, respectively, however, intrinsic gain and transconductance generation factor have nearly 66.66 and 14.28% improvement compared to conventional ED-TFET. Furthermore, the concepts of drain underlapping and dual metal gate have been used to checkout OFF-state current and negative conductance as a final proposal. In addition, this study has also investigated the performance variations in the proposed structure due to the WF change of CG2, length of and position of MS.

This work deals with a distinct concept to realise the junction-less tunnel field effect transistor (JL TFET) by creating the plasma of charges. The crux of this study is to reduce ambipolar conduction and to improve high-frequency figure of merits. To construct a JL TFET, initially silicon film is considered and then metal electrodes are used to form drain and channel region. The drain electrode is separated into two sections and the work function of section adjacent to channel is selected higher than the other section. This provides a non-uniform doping profile in the drain region creating large barrier at the drain/channel junction to prevent the ambipolar conduction. Ambipolarity is reduced to from at . The selection of work function and length of drain electrode adjunct to channel is crucial for optimising device performance. This optimisation provides information that work function >4.0 eV and length = 10 nm completely suppresses the ambipolarity which is around with little degradation in ON-current. The high work function for the section of drain electrode adjunct to channel provides lower gate-to-drain capacitance () and superior high-frequency responses. Furthermore, performance assessment at circuit level is done by implementing primary digital circuits as inverter and NAND logic with lookup table based Verilog-A model.

A novel dual metal gate doping-less vertical tunnel field effect transistor (D-VTFET) on silicon body, using work function engineering is proposed. The proposed structure does not required impurity doping for formation of the drain and the source regions. In this concern, source and drain regions are formed by selecting appropriate work-function of metal electrode. The source and drain regions are not formed by conventional ways of ion implantation or diffusion. Hence, proposed structure is immune greatly to the process variation, issues of doping control and random dopant fluctuations which are serious problems in ultrathin silicon devices. For further improvement in ON state current and analogue/RF figures of merit dual work function of single gate material is considered. The electrical characteristics of the proposed device with the D-VTFET are simulated and compared.

Abruptness at tunnelling junction is a vital issue with doped tunnel field-effect transistor (TFET) to achieve improved electrostatic characteristics. This task is more problematic for charge plasma TFET (CP-TFET) because of large tunnelling barrier at the channel/source interface. In this regard, an effective approach has already been employed through implantation of a horizontal metallic splint (HMS) inside the dielectric region near channel/source joint for improved electrical behaviour of CP-TFET. However, placement of a vertical metal splint (VMS) provides contact for HMS and gate electrode, which gives magnificent analogue/DC characteristics for newer structure. Combination of HMS and VMS (i.e. double metal splint (DMS)) increases electron density at channel/source junction for improved electron tunnelling rate compared with only HMS structure. In this regard, a complete comparative analysis of DMS CP TFET (DMS-CP-TFET) is performed between CP-TFET and HMS-CP-TFET. Furthermore, consequence of length and work-function variation of DMS and HMS on DC/RF parameters is investigated in device optimisation part of this work.