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Inverted bit-line sense amplifier with offset-cancellation capability
Author(s): J. Park, D.-H. Shin, Y.-H. Cho, K.-W. Kwon
Source: Electronics Letters, Volume 52, Issue 9, April 2016, p. 692 - 694
Type: Article
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An inverted bit-line sense amplifier (BLSA) equipped with offset compensation capability for low-power DRAM applications is proposed. The sequential operation of the inverted BLSA allows us to eliminate the edge dummy array in an open bit-line structure resulting in 1.7% less total chip area despite of 10% area penalty of the proposed BLSA occupied by extra switches. For 8-Gb DRAM in 20-nm class technology, the read failure induced by Vth variability is completely removed due to the offset cancellation. The proposed BLSA maintains the gradual increase of the sensing delay when decreasing the power supply down to 0.6 V, while intrinsic read fail prevails below 0.9 V with the conventional one.

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3T-2R non-volatile TCAM with voltage limiter and self-controlled bias circuit
Author(s): C. Kim, K.-W. Kwon
Source:
Type: Article
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A 3T-2R non-volatile ternary content-addressable-memory (nvTCAM) is proposed. Using a voltage limiter and self-controlled bias circuit, both faster match line development and more sensing margin were possible when compared to the conventional nvTCAM. The voltage limiter provides a clear distinction between mismatch cell and ‘don't care’ cell. In case of nvTCAM made of non-volatile memory (NVM) with a large resistance ratio, the sensing delay is reduced by 43.7% thanks to the combination of the self-controlled bias circuit and voltage limiter. The proposed circuit works properly with NVM with resistance ratio as low as 3. The proposed nvTCAM cell was evaluated using a 65 nm CMOS process.

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