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I/O divided column redundancy scheme for high-speed DRAM with multiple I/Os
Author(s): Jae-Goo Lee, Young-Hyun Jun, Chilgee Lee, Bai-Sun Kong
Source: Electronics Letters, Volume 36, Issue 24, November 2000, p. 1996 - 1997
Type: Article
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A novel I/O divided column redundancy (IDCR) scheme that can improve the effectiveness of repair and minimise the overhead of the die area is presented. The IDCR scheme has greater flexibility than conventional schemes in multiple I/O DRAMs. Since an IDCR can share neighbouring redundant column lines (RCLs), the RCLs of neighbouring I/O blocks can be used to repair the defective column lines of a self-block. This work also shows that the IDCR scheme improves the data access speed of normal column lines or redundant column lines by reducing the data bus loading.

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Bit line sensing strategy for testing for data retention faults in CMOS SRAMs
Author(s): V.H. Champac, V. Avendaño, M. Linares
Source: Electronics Letters, Volume 36, Issue 14, July 2000, p. 1182 - 1183
Type: Article
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A strategy for testing for data retention faults in CMOS static random access memories (SRAMs) is proposed. Sensing the voltage at one of the data bus lines with a proper design for testability (DFT) reading circuitry enables the fault-free memory cells from any defective cell(s) to be determined. DFT reading circuitry is also proposed. An analysis of the cost of the proposed approach in terms of area, test time and performance degradation is presented.

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Column redundancy scheme for multiple I/O DRAM using mapping table
Author(s): Yong-Weon Jeon, Young-Hyun Jun, Suki Kim
Source: Electronics Letters, Volume 36, Issue 11, May 2000, p. 940 - 942
Type: Article
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A new column redundancy scheme is presented that can minimise the die area overhead by repair circuits and also achieve fast access speed in high density dynamic random access memories (DRAMs) with wide data widths. The proposed scheme has a large redundancy-area-unit (RAU) which operates a flexible column redundancy scheme that consecutively shifts RDQ (redundant I/O) to neighbouring MDQ (main I/O) without any speed penalty. By using the proposed mapping fuse algorithm, the number of fuses required to store the fail bit address can be reduced, and the chip area reduced.

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Dual TLB structure for supporting two page sizes
Author(s): Jung-Hoon Lee, Jang-Soo Lee, Gi-Ho Park, Kil-Whan Lee, Shin-Dug Kim
Source: Electronics Letters, Volume 36, Issue 8, April 2000, p. 705 - 706
Type: Article
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A new translation lookaside buffer (TLB) structure is proposed which supports dual page sizes so as to obtain the effect of multiple page sizes with high performance and at low cost without operating system support. According to the results of a comparison and analysis, a similar performance can be achieved by using fewer TLB entries compared with conventional TLBs.

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Efficient back-bias generator with cross-coupled hybrid pumping circuit for sub-1.5 V DRAMs
Author(s): Kyeong-Sik Min
Source: Electronics Letters, Volume 36, Issue 7, March 2000, p. 613 - 615
Type: Article
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A very efficient back-bias generator with cross-coupled hybrid pumping circuit (CHPC) is presented. Though the CHPC is based on the previously suggested hybrid pumping circuit (HPC), its cross-coupled nature which can totally eliminate the sacrificial voltage loss in storing the supply voltage (VCC) at the capacitor shows a much better pumping efficiency and increased pumping current over the HPC for VCC ranging from 3.3 to 0.9 V.

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