Digital storage
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- Electrical and electronic engineering [8]
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A new associative memory cell is described and analysed using SPICE3d1. The CMOS cell uses current summation to compute, in parallel, Hamming distances between the search key and each word in the memory. For 32 bit words, SPICE simulations of a 2μm process show a delay of 4ns/bit for Hamming distances less than three.
A single-transistor dynamic random access memory circuit using a GaAs/AlGaAs structure as the storage cell and modulation-doped field-effect transistors for memory accessing and output sensing has been developed. The functionality of the memory is demonstrated and a storage time of 5.4s is measured at room temperature.
An error correction technique is proposed to increase the noise margin of a multivalued MOS memory. The stored voltage information is first converted to a binary representation. The noise margin of the store voltage is then increased by storing and comparing the least significant bits of the binary representation.
Implementation of a winner-take-all (WTA) network suitable for implementing a nearest-match content-addressable memory (CAM) is presented. The resolution of the network in differentiating between words with large bit mismatches is presented. A measure of the time performance of the network is also given. A fully functional 16 word by 12 bit chip has been fabricated through MOSIS using 2 μm double-metal CMOS technology.
The implementation of a capacitive-access CAM cell along with its read/write circuitry are presented. Its advantages over a standard CAM cell are: feasibility of implementing multicell write operation, ready availability of masking of individual bits of a word for the write operation, and a higher order of cell data stability. A fully functional chip has been fabricated through MOSIS using 2 μm double-metal CMOS technology.
A RAM-based auto-associative neural network is described which has several desirable properties, including high storage capacity and absence of minima during recall. The system is implemented as a set of generalising RAM (GRAM) type nodes. The generalisation procedure is described, and comparisons with other types of autoassociator are drawn.
A linear time complexity algorithm to test RAMs is presented. The algorithm requires only 7n read/write operations and provides an extensive fault coverage. The main advantage of the proposed scheme is that a small test time can be achieved.
A three terminal bistable programmable memory cell which can be read either optically or electrically is proposed and demonstrated. The device is based on using Stark effect of the excitonic transitions in a multiquantum well base region of a heterojunction bipolar transistor. The single device can be flipped (and held) from low transmittance (high voltage) to high transmittance (low voltage) state and vice versa by a varying base current signal.
