We measured the impact of the thermoelectric effect, especially the Peltier effect, upon the operation of phase change memory (PCM) in which the contact resistance between the phase change material and the electrode dominates the total resistance. A PCM device having a pillar structure of diameter 500 nm was fabricated using GeCu₂Te₃ (GCT) material. During read operation, the set state (with crystalline PCM) showed ohmic contact between the PCM and the electrode, whereas the reset state (with amorphous PCM) showed Schottky contact. The Schottky contact between the amorphous GCT and the electrode showed a bias polarity dependence of set operation owing to the Peltier effect, which is one of the thermoelectric effects. As PCM devices scale down to the nanometre scale, research on contact resistance and various related effects will become more important.

A novel write bitline (BL) charge sharing write driver (CSWD) and a half- read BL (RBL) pre-charge scheme is presented for a single-ended 8T static random access memory (SRAM). Before write enable (WE) signal assertion, CSWD equalises the write BLs by allowing their charge sharing. Both write BLs are equalised at the middle value of supply voltage using leakage current compensation block. Afterwards, as WE signal is asserted, CSWD produces the rail-to-rail levels at write BL pair. Charging of a BL from half- to essentially reduces the write dynamic power dissipation by 50%. Half- pre-charging is used for RBL to achieve low-power read operation. Read port is powered by virtual ground rail to improve the RBL leakages. The authors compare the proposed 8T design (P8T) with conventional 6T (C6T) and 8T (C8T) designs in a 45 nm technology node. Write power dissipation is reduced by 42% and dynamic read power is reduced by more than 39%. Overall leakages are reduced by more than 18% compared with C6T and ratio of the RBL is improved by more than two orders of magnitude compared with conventional 8T (C8T).

Shifting market trends towards mobile, Internet of things, and data-centric applications create opportunities for emerging low-power non-volatile memories. The attractive features of spin-torque-transfer magnetic-RAM (STT-MRAM) make it a promising candidate for future on-chip cache memory. Two-bit multiple-level cell (MLC) STT-MRAMs suffer from higher write energy, performance overhead, and lower cell endurance when compared with single-level counterpart. These unwanted effects are mainly due to write operations known as two-step (TT) and hard transitions (HT). Here, the authors offer a solution to tackle write energy problem in MLC STT-MRAM by minimising the number of TT and HT transitions. By analysing real applications, it was observed that specific locations within a cache block undergo much more TT and HT transitions resulting in hot locations when compared with other ones (cold locations). These hot locations are more detrimental to the lifetime and reliability of MRAM device. In this work, the authors propose a simple and intuitive dynamic encoding scheme that eliminates all TT and HT at hot locations, hence reducing energy consumption and improving MLC STT-MRAM lifetime. Results on PARSEC benchmarks demonstrate the effectiveness and scalability of the proposed approach to potentially prolong MLC STT-MRAM lifetime.

This Letter proposes a new scheme to eliminate the bit-line leakage current of static random access memory. The proposed scheme utilises a four-input sense amplifier to amplify the voltages of self-compared bit-line pairs. The bit-lines of the proposed structure have no series capacitances and are directly connected to the sense amplifier input. By this way, read delay and error caused by the leakage current of bit-lines will be eliminated. Simulation results in SMIC 28 nm CMOS process design kits show that the proposed scheme has better stability and can decrease delay time by 41.1% at 0.9 V supply voltage compared with the X-Calibration technology.

Fin field-effect transistors (FinFETs) are replacing the traditional planar metal–oxide–semiconductor FETs (MOSFETs) because of superior capability in controlling short channel effects, leakage current, propagation delay, and power dissipation. Planar MOSFETs face the problem of process variability but the FinFETs mitigate the device-performance variability due to number of dopant ions. This work includes the design of static-random access memory (SRAM) cell using FinFETs. The performance analysis of the ST11T, proposed ST13T SRAM cell, and with power gating sleep transistors is given in this study using the Cadence Virtuoso Tool (V.6.1). Owing to its improved gate controllability and scalability, the FinFET transistor structure is better than the conventional planar complementary MOS technology. The proposed design aims at the power reduction and speed improvement for the SRAM cell. From the result it is clear that optimised proposed FinFET-based ST13T SRAM cell is 92% more power efficient with the use of power gating technique, i.e. sleep transistors approach and having 12.84% less delay due to the use of transmission gates in the access path.

Spintronic memory [spin-transfer torque-magnetic random access memory (STT-MRAM)] is an attractive alternative technology to CMOS since it offers higher density and virtually no leakage current. Spintronic memory continues to require higher write energy, however, presenting a challenge to memory hierarchy design when energy consumption is a concern. This study motivates the use of STT-MRAM for the first-level caches of a multicore processor to reduce energy consumption without significantly degrading the performance. The large STT-MRAM first-level cache implementation saves leakage power. Moreover, the use of small level-0 cache regains the performance drop due to STT-MRAM long write latencies. The combination of both reduces the energy-delay product by 65% on average compared with CMOS baseline. The proposed STT hierarchy also shows good scalability over the CMOS with a few benchmarks which scale significantly better. The PARSEC and Splash2 benchmark suites are analysed running on a modern multicore platform, comparing performance, energy consumption and scalability of the spintronic cache system to a CMOS design.

A new pathway to design floating gate quantum dot (QD) non-volatile RAM (QDNVRAM) cells that possess high-speed low-voltage Erase capabilities not possible with conventional floating gate NV memories is presented. This is achieved by directly accessing the QD floating gate layer with an additional drain (D2) during the Erase operation. Experimental data on fabricated long-channel (10 μm/14 μm) QDNVRAM cell shows ‘Erase’ pulse duration of ∼4 μs at voltage of about 10 V using drain D2 which is over two-order smaller than the ‘Write’ pulse value. Quantum mechanical simulations are also presented. QDNVRAM fabrication process is compatible with CMOS processing.

This work investigates the effect of channel engineering on the short channel performance of considered sub-20-nm 3D NAND flash memory. Here, the threshold voltage roll-off (ΔV _th), subthreshold swing and drain induced barrier lowering metrics is studied to evaluate the short channel effects (SCEs) for the examined device. The effect of variation in doping density on SCEs of proposed channel engineered NAND flash memory is also studied. Based on the observation, a thin layer of high doping concentration in the centre of the channel, covering 25% of channel area, has been found to improve the SCE of NAND flash memory compared with the device with uniform channel doping while maintaining sufficient drive current.

In most embedded microprocessor based System on chips (SoCs), cache has become a major source of power consumption due to its increasing size and high access rate. Power optimization of cache based on Compare-based adaptive clock gating (CACG) is proposed to reduce the power waste due to cache idle. By detecting the cache's working state, the CACG can automatically turn off its clock when it is in idle state, saving a large percentage of dynamic power. Measurements of a real SoC chip fabricated under TSMC 65nm CMOS process show that an average of 30.3% power reduction is gained in Dhrystone test benchmark at a cost of negligible area overhead and no virtually performance loss.