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  • Electrical and electronic engineering [4]
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Distributed against centralised crossbar function for realising bank-based multiport memories
Author(s): S. Fukae, T. Inoue, H.J. Mattausch, T. Koide, T. Hironaka
Source: Electronics Letters, Volume 40, Issue 2, January 2004, p. 101 - 103
Type: Article
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The two extreme functionally equivalent possibilities of distributed or centralised crossbar function for realising a bank-based multiport memory are compared on the basis of required global signal and transistor numbers. With respect to both measures, the distributed crossbar function is found to be the better choice for practically relevant multiport-memory configurations.

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Fast quadratic increase of multiport-storage-cell area with port number
Author(s): Y. Tatsumi, H.J. Mattausch
Source: Electronics Letters, Volume 35, Issue 25, December 1999, p. 2185 - 2187
Type: Article
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It is shown that the space required for wordline/bitline routing leads to a quadratic multiport-storage-cell area increase with port number N, dominating from as little as N = 2, N = 6 for small ROM and large SRAM cell types, respectively. Larger N results in enormous area increases (e.g. by a factor of 80 for a 32-port SRAM), making conventional multiport memories unacceptable for most practical applications.

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Hierarchical architecture for area-efficient integrated N-port memories with latency-free multi-gigabit per second access bandwidth
Author(s): H.J. Mattausch
Source: Electronics Letters, Volume 35, Issue 17, August 1999, p. 1441 - 1443
Type: Article
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A two-level hierarchy is exploited for an area-efficient integrated N-port memory architecture, based on 1-port memory cells. The architecture is applicable to all types of dynamic, static and nonvolatile memory. It allows simultaneous read/write access from all ports, with access-rejection probability adjustable to application needs.

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Application of port-access-rejection probability theory for integrated N-port memory architecture optimisation
Author(s): H.J. Mattausch, K. Yamada
Source: Electronics Letters, Volume 34, Issue 9, April 1998, p. 861 - 862
Type: Article
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Area-efficient architectures for integrated N-port memories employ blocks of one port memory cells and dynamic port-to-block connections. The authors determine the block number M necessary to achieve a target port-access-rejection probability for a given port number N and best-case/worst-case conflict-resolve algorithms, by applying stochastic probability theory.

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