This study presents a new energy-efficient design for static random access memory (SRAM) using a low-power input data encoding and output data decoding stages. A data bit reordering algorithm is applied to the input data to increase the number of 0s that are going to be written into the SRAM array. Using SRAM cells which are more energy-efficient in writing a ‘0’ than a ‘1’ benefits from this, resulting in a reduction in the total power and energy consumptions of the whole memory. The input data encoding is performed using a simple circuit, which is built of multiplexers and inverters. After the read operation, data will be returned back to its initial form using a low-power data decoding circuit. Simulation results in an industrial and a predictive CMOS technology show that the proposed design for SRAM reduces the energy consumption of read and write operations considerably for some standard test images as input data to the memory. For instance, in writing pixels of Lenna test image into this SRAM and reading them back, 15 and 20% savings are observed for the energy consumption of write and read operations, respectively, compared with the normal write and read operations in standard SRAMs.

Using conventional memory technologies, for example, static random access memory (RAM) (SRAM), dynamic RAM (DRAM) and flash memory, it is difficult to fulfill the market requirements for higher density and lower power dissipation [1]. Therefore, semiconductor organizations are thinking that it is difficult to supply the expanding market interest for the higher density and lower power nonvolatile memories [2]. The recent invention of memristor device has given hope to semiconductor organizations by offering a less demanding approach to expand the density by utilizing the current fabrication technology [3]. This is conceivable on the grounds that memristor devices just require two terminals to work, which utilize less wafer space, reduce the complexity of circuit interconnections and encourage highdensity integration when used as a part of crossbar structures [4-7]. Besides all these features of memristor, it also has some additional characteristics like low power and non-volatility [8]. But the main limitation of the memristor-based memory cell is its slow write time access [9]. Transmission gate is capable of providing rail-to-rail swing and can easily pass both logic “0” and logic “1” [10]. These advantages help to overcome the problem of slow write time access of memristor. The objective of this chapter is to understand what a memristor is and how can a memristor be modeled for its current-voltage (I-V) characteristics. Further, this chapter deals with the concepts of transmission gates, then using the designed memristor and transmission gates, a DRAM cell was designed. The designed memory cell was simulated using HSPICE tool. The result shows that the memristor-based DRAM cell can replace the conventional memory cell in future to achieve higher density and lower power dissipation.

As the transistor size scales down exponentially to nanometric dimensions, the susceptibility of electronic circuits to radiation increases drastically. Protection against the radiation is important in the field of biomedical, aerospace, communication and computing. Flip-flops (FFs) and static random access memories (SRAMs) are used to store the data in many critical applications where their performance must be resilient to radiation exposures to guarantee reliability. Therefore development of resilient FFs and SRAM are the challenging and demanding problems. In this chapter, different approaches are analysed to design these radiation hard circuits.

This study proposes a single bit-line and disturbance-free static random-access memory (SRAM) cell for ultra-low voltage applications. SRAM cell with read-decoupled and cross-point structure addresses both the read-disturb and half-select stability issues; nevertheless, the write-ability is degraded due to the stacked pass transistors. In this study, the authors propose a single-ended 8T bit-cell and dual word-line control technique that can simultaneously improve the read stability, half-select stability, and write-ability without additional peripheral circuits, which is advantageous for bit-interleaved ultra-low voltage operations. A 4 kb test chip was implemented in a 90 nm complementary metal–oxide–semiconductor process to verify the proposed design. Silicon measurements indicate that the proposed design can operate at a voltage as low as 360 mV with 2.68 μW power consumption.

This study compares the performance and reliability of classical complementary metal-oxide-semiconductor (CMOS) gates with Schmitt trigger (ST) ones. The ST hysteresis, caused by the added positive feedback transistors, improves the design static noise margin (SNM) and offers noise immune operation. Hence, ST-based circuits are expected to operate more reliably than the ones implemented using classical CMOS. Although many research papers have been focused lately on using ST design concepts for implementing more reliable static random access memory (SRAM) cells, significantly less work was devoted to the application of ST concepts in the combinatorial logic domain. Moreover, available research on ST-based logic gates had only focused on the low-voltage/power applications range. The authors are going to look at the whole voltage range and performance spectrum to compare and understand not only the SNMs and the power consumption (at different frequencies and voltage levels) but also the delay and the power-delay-product of ST-based logic gates. These will be compared with classical CMOS as well as with optimally sized CMOS and ST-based logic gates. This study should give a clear picture of the potential advantages ST could offer for combinatorial logic in advanced CMOS technology nodes and of their application range.

This Letter proposes an on-chip data strobe transmission circuit for dynamic random access memory (DRAM). The on-chip differential repeaters with cross-coupled latches are adopted to prevent the sampling margin reduction. A node monitoring circuit has been proposed to prevent short-circuit currents of the on-chip differential repeaters and cross-coupled latches caused by high impedance inputs. When compared with the conventional differential signalling, the proposed circuit can save the short-circuit current of 6.2 mA per a single write operation. The chip has been fabricated in 350 nm CMOS technology and the active chip area is 0.189 mm².

Fin field-effect transistors (FinFETs) are replacing the traditional planar metal–oxide–semiconductor FETs (MOSFETs) because of superior capability in controlling short channel effects, leakage current, propagation delay, and power dissipation. Planar MOSFETs face the problem of process variability but the FinFETs mitigate the device-performance variability due to number of dopant ions. This work includes the design of static-random access memory (SRAM) cell using FinFETs. The performance analysis of the ST11T, proposed ST13T SRAM cell, and with power gating sleep transistors is given in this study using the Cadence Virtuoso Tool (V.6.1). Owing to its improved gate controllability and scalability, the FinFET transistor structure is better than the conventional planar complementary MOS technology. The proposed design aims at the power reduction and speed improvement for the SRAM cell. From the result it is clear that optimised proposed FinFET-based ST13T SRAM cell is 92% more power efficient with the use of power gating technique, i.e. sleep transistors approach and having 12.84% less delay due to the use of transmission gates in the access path.

Soft errors in semiconductor memories occur due to charged particle strikes on sensitive nodes. Technology and voltage scaling increased dramatically the susceptibility of static random access memories (SRAMs) to soft errors. In this study, the authors present AS8-SRAM, a new asymmetric memory cell that enhances the soft error resilience of SRAMs by increasing the cells critical charge. They run Simulation Program with Integrated Circuit Emphasissimulations and system level experiments to validate the AS8-SRAM cell characteristics at circuit level and evaluate the energy and reliability effectiveness of an AS8-SRAM-based cache memory. The authors’ results show that AS8-SRAM presents up to 58 times less failures in time compared to six-transistor SRAM. Moreover, based on embedded benchmarks experimentations, AS8-SRAM achieves up to 22% reduction in energy-delay product without any considerable loss in performance.

A fuzzy static RAM (SRAM) is proposed, which is applicable in fuzzy logic and many multiple-valued logic (MVL) applications. The new structure is basically an extension to the binary SRAM cell. Two cross-coupled voltage mirror circuits are used to be able to hold an arbitrary voltage value. The proposed design forms a robust and reliable structure, which is capable of operating with more than 95% accuracy in spite of imperfect fabrication of carbon nanotube FETs. Another exceptional advantage is its ultra-low-power consumption in MVL environments. It consumes 38.7 and 99% less static power compared with the SRAMs with regular ternary and quaternary components, respectively.

A ferroelectric-gated graphene field-effect transistor was fabricated by consecutively stacking two distinct graphene–ferroelectric hybrid ribbons at right angles. Two graphene layers play different roles. One graphene layer acts as a gate electrode and the other graphene layer acts as a channel between two electrodes, source and drain. Electric gating at the gate graphene modulates the resistance of the channel graphene. By means of ferroelectric polarisation, bistable resistance states of the channel graphene could be recorded, and the retention time of bistability was estimated to be 460 days by extrapolating of two resistance values in time–resistance relationships. Furthermore, the underlying concept to fabricate bistable memory device was extended to the methodology to realise a logic-gate device by stacking three distinct graphene–ferroelectric hybrid ribbons.

As the scale of graphene-based non-volatile memory is reduced, the ratio of access resistance R _A to total channel resistance R _TOT is increased. To investigate the effect of the R _A on I–V characteristics, we fabricated devices with various access lengths L _A and self-aligned structure. Proposed structure using self-aligned gate minimises L _A, and thereby improves the drain current, ‘on/off’ current ratio I _ON/I _OFF and transfer characteristics. In proposed structure, ‘off’ current is increased from 0.16 to 0.28 mA because R _TOT was reduced; ‘on’ current increased from 0.35 to 0.72 mA, but I _ON/I _OFF increased from 2.18 to 2.57. Proposed structure also had larger memory window (8.5 V) than did conventional devices (6.7 V).

Six-transistor static random-access memory (6T SRAM) cell is the fundamental building block of memory cache in modern microprocessors. Each bit of data is stored in an individual 6T SRAM cell in the memory subsystem. Read data stability and write ability of 6T SRAM cells are degraded with the scaling of CMOS technology. Conventional circuit techniques for achieving wider voltage margins during read and write operations cause significantly larger silicon area and increased power consumption. Several alternative FinFET memory design techniques are presented in this chapter for achieving stronger data stability during read operations and wider voltage margin during write operations without causing area and power consumption overheads in the memory subsystems of microprocessors.

Operation of the 1-transistor, 1-capacitor dynamic random access memory cell that allows for two-bit operation, double the typical storage capacity, is explored. By using a metal-ferroelectric-semiconductor field-effect transistor, a second bit is captured in the ferroelectric layer polarisation resulting from negative and positive polarisation states. As a result, new modes of operation are created giving non-volatile, long-term storage as well as decreased power consumption and radiation hardening. A typical write and read operating cycle is outlined in-depth and used to verify operation indicating four distinct states representing the two bits. The resulting empirical data gives a comprehensive presentation of the read cycle of the memory cell. Methods for determining the polarisation state of the transistor are also explored and used to determine the average value for measured channel resistance using three types of transistors, each having different channel width and length.

Quantum dot gate field-effect transistor (QDGFET) generates three states in their transfer characteristics. A successful model can explain the generation of third state in the transfer characteristics of the QDGFET. The innovative circuit design using QDGFET can be used to design different ternary logic. This Letter discusses the design of ternary logic static random access memory using QDGFET.

In this paper, a new voltage mirror circuit by using carbon nanotubes (CNTs) technology is presented. This circuit is specifically proposed for the application of duplicating multiple-valued and fuzzy dynamic random access memories. The given structure prevents any voltage drop for the capacitor inside the memory cell. As a result, any fanout circuit can be driven. The new structure can be utilised for different multiple-valued logic systems without a change. The unique characteristics of carbon nanotube field effect transistor (CNFET) technology are exploited in this paper to meet the desired design goals. It demonstrates the potentials of CNFET technology in a realistic very large-scale integration application. The proposed design is highly tolerant to D _CNT variation and it is also immune to misaligned CNTs. Simulation results demonstrate that it provides sufficient driving capability with reasonable accuracy.

This study documents the speeds of various SRAM buffer memories that are possible in a contemporary fast SiGe heterojunction bipolar transistor (HBT) BiCMOS process. An SRAM in a 0.13 µm HBT BiCMOS technology using current mode logic (CML)-style circuits serves as a basis for the discussion. This basic SRAM design features a CML decoder, CML word line driver, bipolar sense amplifier for achieving high speed and CMOS 6T memory cells for high density. The BiCMOS technology is especially useful for realising ultra-high-speed SRAMs for low level cache memory in high-clock rate computer systems, but when reorganised can also be utilised in analogue-to-digital converter (ADC) systems to store digitalised data. Speed and power tradeoffs can be made using different bias strategies, CML logic levels and different generations of SiGe HBTs. A demonstrated 128 kb SRAM macro consumes 2.7 W at 4 GHz using a −3.4 and −1.5 V supply voltage for the bipolar and CMOS circuits, respectively, and has dimensions of 3.5 mm × 3.6 mm by using IBM 8HP SiGe technology, which provides an HBT with a f _T of 210 GHz. This macro can be integrated into large scale, ultra-wide bus SRAMs using heterogeneous silicon and 3D technology. Simulation indicates that with the next generation of SiGe HBTs, this SRAM macro can operate at 5 GHz, while consuming the same amount of power or alternatively consume 0.73 W, which is 73% less power consumption compared to 8HP, while operating with the same frequency of 4 GHz. Reorganising the memory for a 4 way-interleaved ADC, it can accept data written at 9.5 GS/s for 8HP designs, and 11.9 GS/s for 8XP designs.

This paper presents a highly integrated sinusoid reference generating system based on Microblaze, suitable for precise testing of protective relays. Microblaze, a soft CPU core, was embedded in a FPGA that integrates an ADC interface, a DAC interface, an EEPROM and other peripherals. The prototype and transfer functions of various types of digital filters were designed with reference to the characteristic of the required output signal. Their functional behaviour were implemented in the system on chip using a recursion algorithm. As a critical factor in the digital reference design, a detailed discussion has been performed to introduce the theory of three types of closed-loop control, i.e. amplitude, frequency and phase control. A digital PI control algorithm was implemented in the system to satisfy the control target. The experimental results indicate that the relay evaluation system, using this sinusoid reference, operates correctly. The paper will demonstrate how the performance of the output sine signal improves, as compared with the normal sine reference, especially when outputting low amplitude signals. The research methodology of this reference system and this highly integrated circuit are significant for the optimization of a relay testing system, and provide a theoretical justification and a feasible implementation for a precise relay testing system.

A design for an integer motion estimator of high-efficiency video coding (HEVC) is presented. HEVC supports the 64 × 64 coding tree unit, the recursive quad-tree coding unit structure and the asymmetric motion-partitioning mode in a high compression ratio. These features require a structure of integer motion estimation that is more complex than that of H.264/AVC. The new structures of a memory read controller and a sum of absolute difference (SAD) summation block are proposed. The new memory read controller reduces the internal memory read time, and the new SAD summation block structure supports the recursive quad-tree coding unit structure and the asymmetric motion-partitioning mode. The proposed design is implemented in Verilog HDL and synthesised using the 65 nm CMOS technology. The gate count is 3.56 M, and the internal static random access memory is about 20 kbyte. The operation frequency is 250 MHz when a 4 K-Ultra high definition (UHD) (3840 × 2160P at 30 Hz) sized video is encoded.

Gain-cell-based embedded dynamic random-access memory (DRAMs) are a potential high-density alternative to mainstream static random-access memory (SRAM). However, the limited data retention time of these dynamic bitcells results in the need for power-consuming periodic refresh cycles. This Letter measures the impact of body biasing as a control factor to improve the retention time of a 2 kb memory block, and also examines the distribution of the retention time across the entire gain-cell array. The concept is demonstrated through silicon measurements of a test chip manufactured in a logic-compatible 0.18 μm CMOS process. Although there is a large retention time spread across the measured 2 kb gain-cell array, the minimum, average and maximum retention times are all improved by up to two orders of magnitude when sweeping the body voltage over a range of 375 mV.

An antifuse structure that is fully compatible with the standard floating-gate technology is presented. The antifuse consists of an oxide-nitride-oxide dielectric layer, sandwiched between polysilicon and N-well layers. The characteristics of the antifuse are investigated. The off-state resistance of the antifuse is larger than 10 GΩ. The programmed antifuses show linear ohmic characteristics and have a tight resistance distribution centred around 350 Ω. The time dependent dielectric breakdown measurements show that the extrapolated lifetime of the unprogrammed antifuse at 5.5 V is as long as 40 years, and the resistance change of post-program antifuses under the continuous reading mode test is lower than 5%.

The fabrication of gallium oxide nanodots for the application of resistive random access memory (RRAM) using a process of atomic force microscopy (AFM) local anodic oxidation on an indium tin oxide conductive glass substrate is reported. In the atmospheric environment, an AFM probe tip contacts the gallium film locally. This gallium oxide nanodot acts as the insulator layer in a single unit of the RRAM. The structure describes the insulator layer (GaOx) sandwiched by the top (AFM tip) and bottom (Ga film) electrodes. Using current and voltage biased methods, the device switches from a high-resistance state (HRS) to a low-resistance state (LRS) and reset from LRS to HRS. Low read-voltage is used to distinguish the high/low resistance to present the digital data. Presented results show the ability of atomic force microscopy anodic oxidation to produce 300 nm diameter gallium oxide nanodots on glass substrates for potentially high density RRAMs.

This undergraduate textbook for electrical and computer engineering students is dedicated solely to digital CMOS electronics. It covers many of the topics of graduate level textbooks, but in an introductory style specifically crafted (and course tested) for undergraduates. Students will not need a prerequisite in analog electronics, allowing instructors flexibility in course scheduling. This book blends the academic and industrial experience of the authors to define a base of electronics instruction for the CMOS chip industry. CMOS Digital Integrated Circuits: A First Course teaches the fundamentals of modern CMOS technology by focusing on central themes and avoiding excessive details. Extensive examples, self-exercises, and end-of-chapter problems assist in teaching the current practices of industry and subjects taught by graduate courses in microelectronics. Computer engineering curriculums can remove the analog electronics prerequisite altogether when adopting this book. Key Features: CMOS technology written specifically for (and tested by) undergraduates; Equal treatment to both types of MOSFET transistors that make up computer circuits; Power properties of logic circuits; Physical and electrical properties of metals; Introduction of timing circuit electronics; Introduction of layout; Real-world examples and problem sets.

Researchers from the Jeju National University in Korea have proposed a method for depositing titanium dioxide (TiO₂) films onto flexible polymer substrates. The method, known as electrohydrodynamic printing, has been used in other printed circuit technology, and the group have used the technique's advantages to improve the manufacture of flexible memory devices.Titanium dioxide was the compound used to manufacture the first solid-state memristor device in 2008, and this technology is advancing rapidly, with commercial devices expected within the next few years. Memristor based memory is known as non-volatile storage, as the memory elements maintain their state even in the absence of power, which has obvious advantages for efficiency, cost and environmental concerns.While memristors have clear uses for standard solid-state storage, when combined with flexible substrates they can also be applied to other thin-film technology, such as solar cells, keypads and displays.

Sphere-shaped-recess cell-array transistors (S-RCATs) have been playing a major role in DRAMs on the 70 nm design-rule. The S-RCAT has a recessed-channel structure that produces small drain-induced barrier lowering (DIBL) and large body-bias effect. The temperature and body-bias dependence of DIBL is studied for a S-RCAT. Negative DIBL is peculiarly observed under certain conditions. It is assumed that the negative DIBL originates from the increase of body-bias effect with increasing drain bias and temperature.

This paper introduces a novel hardware architecture for modular exponentiation. The proposed architecture is optimised for circuit area sensitive applications such as resource-constrained mobile devices in ubiquitous computing. The architecture provides a scalable design suitable for both the RSA and Diffie-Hellman cryptosystems. This architecture has been implemented on UMC 0.13μm CMOS standard cell technology. The 1,024-bit design utilises only 3,188 gates and 3,072 RAM bits. The 2,048-bit design consumes only 4,275 gates and 6,144 RAM bits. To the authors' knowledge, the proposed architecture achieves the smallest area in comparison to other candidates reported in the literature. The 1,024-bit design reports the lowest power consumption of [email protected] (5 pages)