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Digital storage

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  • Electrical and electronic engineering [4]
  • Circuit theory and circuits [4]
  • Electronic circuits [4]
  • Digital electronics [4]
  • Memory circuits [4]
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  • 1985 [4]

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Novel MOS memory for serial signal processing applications
Author(s): D.S. McGrath, D.J. Myers
Source: Electronics Letters, Volume 21, Issue 24, November 1985, p. 1170 - 1171
Type: Article
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A novel serial memory is reported, based on an array of MOS three transistor cells, which does not require serial-parallel data format convertors on the input and output. It can be used to realise compact, low-power delay elements of programmable length and is suitable for application in serial digital signal processing integrated circuits.

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Optically induced latch-up and other effects in CMOS UVEPROMs
Author(s): D.J. Hinds, J.C.D. Stokoe
Source: Electronics Letters, Volume 21, Issue 13, June 1985, p. 553 - 554
Type: Article
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Photographic flash-gun equipment used close to uncovered CMOS UVEPROMs can induce a variety of different failure modes including: (a) destructive latch-up, (b) transients in the output logic levels and in the supply current and (c) a nonde structive ‘output latching’ effect. The mode of failure observed depends on the level of illumination used and on the logic state of the output pins.

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Experimental 1 Mbit DRAM using power reduction techniques
Author(s): Katsutaka Kimura, Kiyoo Itoh, Ryoichi Hori, Jun Etoh, Yoshiki Kawajiri
Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 132, Issue 1, 1985 , p. 23 - 28
Type: Article
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One of the serious problems which must be overcome in realising a 1 Mbit DRAM is high-power dissipation associated with data-line charging and discharging. To solve this problem, this paper proposes the following three techniques, which permit power reduction by about one-quarter: a multidivided data-line structure, 512 refresh cycles and an on-chip voltage limiter circuit. These techniques are proven to be useful through the design and evaluation of an experimental n-MOS 1 Mbit DRAM with a 46 mm2 chip size. The chip fabricated provides a 295 mW operating power at a 260 ns cycle time despite the fast access time of 90 ns. The possibility of further power reduction is also described.

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Alpha-particle-induced failure modes in dynamic RAMs
Author(s): P.M. Carter, B.R. Wilkins
Source: Electronics Letters, Volume 21, Issue 1, January 1985, p. 38 - 39
Type: Article
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The alpha-particle-induced soft error rates of 64K D-RAMs made by five leading manufacturers have been compared. Different samples from the same manufacturer, and those from four different manufacturers, are all shown to be very similar, but the fifth manufacturers product has a soft error rate that is an order of magnitude larger than the others. The results also suggest that, for most products, sensitivity is in the bit lines or sense amplifiers, while for those from the fifth manufacturer it resides in the cells.

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