Digital storage
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A gain cell embedded dynamic random access memory (eDRAM) with a noble charge injection technique is presented. The gain memory cell is composed of dual-threshold two logic N-type MOSs implemented in a generic triple-well CMOS process. A negative-voltage toggle on the parasitic junction diode formed between the pocket p-well and the cell data node couples up the cell storage voltages. It results in a much enhanced retention time in a compact bit area. Moreover, the technique exhibits much strong immunity from the write disturbance. Measured results at 85°C from a 110 nm 64 kbit prototype eDRAM incorporating the proposed technique demonstrate 69% enhanced retention time and 86% smaller write disturbance loss compared with the conventional one.
Quantum dot gate field-effect transistor (QDGFET) generates three states in their transfer characteristics. A successful model can explain the generation of third state in the transfer characteristics of the QDGFET. The innovative circuit design using QDGFET can be used to design different ternary logic. This Letter discusses the design of ternary logic static random access memory using QDGFET.
The presence of voltage controlled negative differential resistance was observed in conduction characteristics recorded at room temperature for 300 nm thick spin-coated films of graphene oxide (GO) sandwiched between indium tin oxide (ITO) substrates and top electrodes of sputtered gold (Au) film. The GO crystallites were found from the X-ray diffraction studies to have an average size in the order of 7.24 nm and to be preferentially oriented along (001) plane. Raman spectroscopy suggested that the material consisted of multilayer stacks with the defects being located at the edges with an average distance of 1.04 nm apart. UV visible spectroscopy studies suggested that the band gap of the material was 4.3 eV, corresponding to direct transitions. The two-terminal ITO/GO/Au devices exhibited memristor characteristics with scan-rate dependent hysteresis, threshold voltage and On/Off ratios. A value of >104 was obtained for On/Off ratio at a scan rate of 400 mVs−1 and 4.2 V.
In this paper, a new voltage mirror circuit by using carbon nanotubes (CNTs) technology is presented. This circuit is specifically proposed for the application of duplicating multiple-valued and fuzzy dynamic random access memories. The given structure prevents any voltage drop for the capacitor inside the memory cell. As a result, any fanout circuit can be driven. The new structure can be utilised for different multiple-valued logic systems without a change. The unique characteristics of carbon nanotube field effect transistor (CNFET) technology are exploited in this paper to meet the desired design goals. It demonstrates the potentials of CNFET technology in a realistic very large-scale integration application. The proposed design is highly tolerant to D CNT variation and it is also immune to misaligned CNTs. Simulation results demonstrate that it provides sufficient driving capability with reasonable accuracy.
Multiple way tables in which items can be placed on several buckets are used in many computing applications. Some examples are cache memories and multiple hash tables structures. In most cases, the items are stored in electronic memories that are prone to soft errors that can corrupt the stored items. To avoid data corruption, memories can be protected with a parity bit or with an error correction code. It is shown that most single bit errors can be detected in multiple way tables without adding a parity bit. This can be done by placing the items in a predetermined order in the multiple ways of the table.
