SRAMs in nanoscale CMOS technology suffer from plethora of design challenges such as increased process variation, increased leakage current and variation in the cell current that threatens the reliability of sensing scheme. These issues coupled with continuous increase in the SRAMs size, requires additional techniques and treatments such as read-assist techniques to ensure fast and reliable read operation. In this study, the authors address these concerns and propose a novel read-assist sensing scheme. The circuit is simulated using Spectre in 65 nm CMOS technology. Simulation results showed an increased sensing speed, lower power dissipation and enhanced SRAM dynamic cell stability. A complete comparison is made between the proposed scheme, the conventional circuit and another state of the art design, which shows speed improvement of 55.34, 66.01% and power reduction of 21.33, 89.09% with respect to conventional sense amplifier and the referenced scheme, respectively. These enhancements are at the expense of negligible area overhead. Also, the proposed scheme enables one to reduce the cell's V_DD by 227 and 345 mV for the same operating frequency with respect to conventional and referenced circuits, respectively. This results in leakage power reduction of 19.7 and 30% which constitutes a considerable portion of overall power dissipation in nanoscale SRAMs.

The study presents the dependence of floating gate (FG) coupling potential, V_FG on the source line (SL) programming voltage, V_SL of the split-gate flash memory cells with an additional top coupling gate above FG, called the ‘SG-TCG’ cells. The mathematical analysis shows non-linear V_FG against V_SL behaviour of SG-TCG cells depending on the operation region of FG-MOSFETs. It is found that as the value of V_SL increases, the value of V_FG initially increases steeply, then gradually and finally, linearly with a lower slope. This anomalous V_FG against V_SL behaviour is because of the potential drop in the bulk of FG-MOSFETs by the applied V_SL. The mathematical analysis, also, shows SL coupling factor (κ_SL) roll-off because of the increase in the FG-MOSFETs body potential with the increase in V_SL. In addition, κ_SL is shown to approach a constant value in the saturation region of FG-MOSFETs where V_FG is less susceptible to supply voltage fluctuation. The mathematical analysis agrees very well with the numerical device simulation. The study, clearly, shows that in order to achieve higher shift in programme cell threshold voltage and reduce performance variability owing to supply voltage fluctuation, the target programming bias V_SL of nanoscale SG-TCG cells must be higher than the saturation voltage of FG-MOSFETs.

The increased device variations, lower supply voltages have enforced the usage of write-assist circuits in static random access memory (SRAMs) in the nano-complementary metal oxide semiconductor (CMOS) regime. Negative bit-line scheme during write has been found one of the most promising write-assist solutions. A new low power, negative bit-line scheme is presented. The presented negative bit-line technique can be used to improve the write ability of 6 T single-port (SP) as well as 8 T dual-port (DP) and other multiport SRAM cells. Negative voltage is generated on-chip using capacitive coupling. Only the bit-line on which a ‘0’ is to be written is taken negative during write operation. The proposed circuit design topology does not affect the read operation for bit-interleaved architectures enabling high-speed operation. Simulation results and comparative study of the present scheme with state-of-the art conventional schemes proposed in the literature for 45 nm CMOS technology show that the proposed scheme is superior in terms of process-variations impact, area overhead, timings and dynamic power consumption.