This article presents a review of physical, analytical, and compact models for oxide-based RRAM devices. An analysis of how the electrical, physical, and thermal parameters affect resistive switching and the different current conduction mechanisms that exist in the models is performed. Two different physical mechanisms that drive resistive switching; drift diffusion and redox which are widely adopted in models are studied. As for the current conduction mechanisms adopted in the models, Schottky and generalised hopping mechanisms are investigated. It is shown that resistive switching is strongly influenced by the electric field and temperature, while the current conduction is weakly dependent on the temperature. The resistive switching and current conduction mechanisms in RRAMs are highly dependent on the geometry of the conductive filament (CF). 2D and 3D models which incorporate the rupture/formation of the CF together with the variation of the filament radius present accurate resistive switching behaviour.

The presence of voltage controlled negative differential resistance was observed in conduction characteristics recorded at room temperature for 300 nm thick spin-coated films of graphene oxide (GO) sandwiched between indium tin oxide (ITO) substrates and top electrodes of sputtered gold (Au) film. The GO crystallites were found from the X-ray diffraction studies to have an average size in the order of 7.24 nm and to be preferentially oriented along (001) plane. Raman spectroscopy suggested that the material consisted of multilayer stacks with the defects being located at the edges with an average distance of 1.04 nm apart. UV visible spectroscopy studies suggested that the band gap of the material was 4.3 eV, corresponding to direct transitions. The two-terminal ITO/GO/Au devices exhibited memristor characteristics with scan-rate dependent hysteresis, threshold voltage and On/Off ratios. A value of >10⁴ was obtained for On/Off ratio at a scan rate of 400 mVs⁻¹ and 4.2 V.

Gain-cell-based embedded dynamic random-access memory (DRAMs) are a potential high-density alternative to mainstream static random-access memory (SRAM). However, the limited data retention time of these dynamic bitcells results in the need for power-consuming periodic refresh cycles. This Letter measures the impact of body biasing as a control factor to improve the retention time of a 2 kb memory block, and also examines the distribution of the retention time across the entire gain-cell array. The concept is demonstrated through silicon measurements of a test chip manufactured in a logic-compatible 0.18 μm CMOS process. Although there is a large retention time spread across the measured 2 kb gain-cell array, the minimum, average and maximum retention times are all improved by up to two orders of magnitude when sweeping the body voltage over a range of 375 mV.

There are a number of satellites working in the harsh space environment. The charged particles in space may strike the electron devices causing the undesired influences, such as soft errors in memory devices or permanent damage in hardware circuits. Aiming at reliability evaluation of very-large-scale integration circuits implemented in SRAM-based field programmable gate arrays, a fault injection platform is constructed based on the soft error mitigation controller in this study. The authors adopt a 16K-point fast Fourier transformation processor as the design under test (DUT) and inject errors into different positions. The effectiveness of this platform is varied by comparing the results of DUT with Golden data. Compared with the traditional reliability testing techniques, the fault injection method proposed in this study has the advantages of low cost, short test period and low resource consumption. Hence, the proposed fault injection design is suitable for circuits consuming huge resources and large number of repeating tests.