http://iet.metastore.ingenta.com
1887

Digital storage

More general concepts than this:

More specific concepts than this:

1-1 of 1 results

Filter by subject:

< Any subject

Filter by content type:

Filter by publication date:

< Any publication date

  • 2017 [1]

Filter by author:

< Any author

Low-power and high-speed 13T SRAM cell using FinFETs
Author(s): Shilpa Saxena, Rajesh Mehra
Source: IET Circuits, Devices & Systems, Volume 11, Issue 3, 2017 , p. 250 - 255
Type: Article
+ Show details - Hide details

Fin field-effect transistors (FinFETs) are replacing the traditional planar metal–oxide–semiconductor FETs (MOSFETs) because of superior capability in controlling short channel effects, leakage current, propagation delay, and power dissipation. Planar MOSFETs face the problem of process variability but the FinFETs mitigate the device-performance variability due to number of dopant ions. This work includes the design of static-random access memory (SRAM) cell using FinFETs. The performance analysis of the ST11T, proposed ST13T SRAM cell, and with power gating sleep transistors is given in this study using the Cadence Virtuoso Tool (V.6.1). Owing to its improved gate controllability and scalability, the FinFET transistor structure is better than the conventional planar complementary MOS technology. The proposed design aims at the power reduction and speed improvement for the SRAM cell. From the result it is clear that optimised proposed FinFET-based ST13T SRAM cell is 92% more power efficient with the use of power gating technique, i.e. sleep transistors approach and having 12.84% less delay due to the use of transmission gates in the access path.

Add to favourites
Export citations
Items per page 20 | 50 | 100
Print this page
This is a required field
Please enter a valid email address