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Self-compared bit-line pairs for eliminating effects of leakage current
Author(s): Jingbo Zhang, Jinkai Wang, Chunyu Peng, Xuan Li, Zhiting Lin, Xiulong Wu
Source: Electronics Letters, Volume 53, Issue 21, October 2017, p. 1396 - 1398
Type: Article
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This Letter proposes a new scheme to eliminate the bit-line leakage current of static random access memory. The proposed scheme utilises a four-input sense amplifier to amplify the voltages of self-compared bit-line pairs. The bit-lines of the proposed structure have no series capacitances and are directly connected to the sense amplifier input. By this way, read delay and error caused by the leakage current of bit-lines will be eliminated. Simulation results in SMIC 28 nm CMOS process design kits show that the proposed scheme has better stability and can decrease delay time by 41.1% at 0.9 V supply voltage compared with the X-Calibration technology.

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Read-decoupled 8T1R non-volatile SRAM with dual-mode option and high restore yield
Author(s): Zhiting Lin, Yong Wang, Chunyu Peng, Wenjuan Lu, Xuan Li, Xiulong Wu, Junning Chen
Source:
Type: Article
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This Letter proposes a read-decoupled (RD) and average 8T1R non-volatile static RAM (SRAM), RD-8T1R. It uses only one memristor to achieve store energy reduction and higher restore yield compared with other two memristors based non-volatile SRAMs. In addition, this structure can offer two alternative SRAM modes unlike previously known non-volatile SRAMs, i.e. a high speed and a stable mode. Compared with existing technologies, the simulation results in TSMC-65 nm show that the proposed scheme provides a remarkable restore yield. There are 154% improvement in the read static noise margin (@typical–typical (@TT) corner and stable mode) and 23% improvement in the read delay (@TT corner and high speed mode) compared with the previous 6T/7T/8 T non-volatile SRAMs.

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