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Three Digital Closed Loops Reference Generating Platform for Protective Relay Testing
Author(s): Wenwen Zhou, Qian Xiang, Zhichuan Wei, Rui Yu
Source: 12th IET International Conference on Developments in Power System Protection (DPSP 2014), 2014, p. 12.85 - 12.85
Type: ConferencePaper
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This paper presents a highly integrated sinusoid reference generating system based on Microblaze, suitable for precise testing of protective relays. Microblaze, a soft CPU core, was embedded in a FPGA that integrates an ADC interface, a DAC interface, an EEPROM and other peripherals. The prototype and transfer functions of various types of digital filters were designed with reference to the characteristic of the required output signal. Their functional behaviour were implemented in the system on chip using a recursion algorithm. As a critical factor in the digital reference design, a detailed discussion has been performed to introduce the theory of three types of closed-loop control, i.e. amplitude, frequency and phase control. A digital PI control algorithm was implemented in the system to satisfy the control target. The experimental results indicate that the relay evaluation system, using this sinusoid reference, operates correctly. The paper will demonstrate how the performance of the output sine signal improves, as compared with the normal sine reference, especially when outputting low amplitude signals. The research methodology of this reference system and this highly integrated circuit are significant for the optimization of a relay testing system, and provide a theoretical justification and a feasible implementation for a precise relay testing system.

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Scaling Modular Exponentiation Hardware to the Minimum
Author(s): Xiaolin Cao, M. O'Neill
Source: IET Irish Signals and Systems Conference (ISSC 2012), 2012, p. 79 - 79
Type: ConferencePaper
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This paper introduces a novel hardware architecture for modular exponentiation. The proposed architecture is optimised for circuit area sensitive applications such as resource-constrained mobile devices in ubiquitous computing. The architecture provides a scalable design suitable for both the RSA and Diffie-Hellman cryptosystems. This architecture has been implemented on UMC 0.13μm CMOS standard cell technology. The 1,024-bit design utilises only 3,188 gates and 3,072 RAM bits. The 2,048-bit design consumes only 4,275 gates and 6,144 RAM bits. To the authors' knowledge, the proposed architecture achieves the smallest area in comparison to other candidates reported in the literature. The 1,024-bit design reports the lowest power consumption of [email protected] (5 pages)

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Next-generation memory: the realisation of a new market opportunity?
Author(s): G. Schmergel
Source: 1st IEE International Conference on: Commercialising Technology and Innovation, 2005, p. 2 - 2
Type: ConferencePaper
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A collection of slides from the author's conference presentation on the use of carbon nanotubes for memories is given. (6 pages)

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Design of an efficient interface between an FPGA and external memory
Author(s): F. Crowe, A. Daly, T. Kerins, W. Marnane
Source: Irish Signals and Systems Conference 2004, 2004, p. 118 - 123
Type: ConferencePaper
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The interface between an FPGA core design and its communicating system is often the limiting factor in achieving high performance. The paper looks at how the memory interface logic can be separated from the core design, allowing the cores to run at frequencies greater than the maximum memory access frequency. FIFO memory blocks are used as buffers to transfer data between different clock domains. An application example implementing a number of encryption algorithms on an FPGA is provided. The complete design is prototyped on a PCI accelerator card containing a Xilinx Virtex-E2000 FPGA and SRAM memory banks.

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A 400 Mbps 1394 disk controller IC with integrated DRAM
Author(s): S. Killeen, F. Buckley, K. Butler, T. Kiely, P. Gillen, P. McCarthy, C. Fewer, T. Carter, D. Moloney, C. Cahill, C. Whyte, M. Harkin, F. Brosnan, G. Byrne, V. Fraisse, P. Mougeat, M. Schulze, G. Moller, J. Wach
Source: IEE Colloquium on Systems on a Chip, 1998, p. 15 - 15
Type: ConferencePaper
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A 400 Mbps, 1394 Disk Controller IC, with 0.75 Mbits of integrated DRAM, in a 0.35 μm 5 layer metal CMOS ASIC process is presented. The device makes use of a variety of circuit techniques, to achieve 5 V tolerance, and low jitter clock generation as well as 40 MIPs operation for the embedded RISC. The device provides a flexible architecture which can be easily extended to 800+ Mbps by integrating the 1394 physical layer (PHY) transceivers. (2 pages)

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Animate vision demonstrator utilising reconfigurable system designs
Author(s): A.J. Shelley, N.L. Seed
Source: Fifth International Conference on Image Processing and its Applications, 1995, p. 500 - 504
Type: ConferencePaper
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The justifications for migration from discrete logic implementations to field programmable devices (PLD/FPGA) for state machine, logic replacement and datapath operations are well known and established. They offer the user a flexible design methodology at a gate level for a low initial investment and demand no early commitments to high volumes. Furthermore, the capabilities of a volatile static memory based FPGA technology extend well beyond the limited scope of integration enhancement. This paper outlines a reconfigurable image processing architecture (RIPA) and its integration into an animate vision demonstrator.

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