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Animate vision demonstrator utilising reconfigurable system designs
Author(s): A.J. Shelley, N.L. Seed
Source: Fifth International Conference on Image Processing and its Applications, 1995, p. 500 - 504
Type: ConferencePaper
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The justifications for migration from discrete logic implementations to field programmable devices (PLD/FPGA) for state machine, logic replacement and datapath operations are well known and established. They offer the user a flexible design methodology at a gate level for a low initial investment and demand no early commitments to high volumes. Furthermore, the capabilities of a volatile static memory based FPGA technology extend well beyond the limited scope of integration enhancement. This paper outlines a reconfigurable image processing architecture (RIPA) and its integration into an animate vision demonstrator.

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