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Digital storage

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  • A. T. Erozan [1]
  • B. Tavli [1]
High performance adjacent error detection for nanometer devices
Author(s): A. T. Erozan, B. Tavli
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Type: Article
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Static random-access memory (SRAM) based memories are widely used in electronic systems and if their contents change due to external reasons, the electronic system can functionally fail. One of the external reasons is the radiation induced soft errors as the SRAM memories are susceptible to radiation effects. Majority of the recently proposed methods use error correction codes (ECC) to mitigate soft errors. Error correction/detection capabilities of such methods are at most 3 bits in a codeword which will be insufficient while number of memory bits affected by a radiation particle is increased, as CMOS process technology shrinks towards around 5 nm. Since memory bits affected by a radiation particle are physically close, adjacent error detection/correction becomes a hot research topic. In this Letter, Euclidean geometry-low density parity check code, more capable ECC than Hamming code used in recent works, is explored in context of adjacent error detection performance. The results show that proposed method successfully detects up to 14-bit adjacent errors in a 15-bit codeword. As such, this method is suitable where high detection performance is needed. The proposed method is also simplified for efficient hardware implementation while detection performance is not sacrificed. Both methods are compared in terms of resource usage.

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