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Flash-type EEPROMs were fabricated for the first time by in situ multiple rapid thermal processing (RTP) modules. In the Letter, rapid thermal oxynitridation tunnel oxide (RTONO) formation followed by in situ arsenic (As)-doped floating gate polysilicon growth by rapid thermal chemical vapour deposition (RTCVD) were introduced. The flash cell indicates only 20% narrowing of the Vt window after 5 × 104 program/erase cycle stress. Moreover, there is a higher breakdown field of the ONO film on the floating-gate polysilicon film owing to extremely flat poly-Si surface. Thus, the in situ multiple RTP technology is the key for future flash memory fabrication processes.
The paper describes a new architecture for a split-gate flash EEPROM memory array. The new array architecture provides increased speed and less susceptibility to soft writes during read operations. A unique circuit design and operation method obviates the need for applying high erase voltage in the path between the memory array and the sense amplifier. This allows all the transistors in this speed path to be fabricated as low voltage minimum channel length devices, thereby increasing their speed of operation and consequently the speed of the memory device as a whole. The new architecture, however, requires the addition of two extra rows of nonmemory cell transistors in addition to following a strict programming sequence to guard against spurious programming of unselected cells.
A novel high-speed sense amplifier for use with nonvolatile single-transistor memory cells is described. Using a current-sensing scheme and novel circuit techniques, the amplifier achieves sensing speeds equal to or better than those achievable by memory arrays using two transistors per cell. Other circuit techniques were used to improve the circuit-noise immunity as well as sensitivity to critical mask misalignments including the use of output latches, dummy bit lines and decoded odd/even reference-memory-cell selection. The circuit was implemented on a 32 k EPROM memory chip using 1.5 µmN-well CMOS process.
A single-electron memory cell, in which one bit of information is represented by +n and −n electron number states, is described. An experimental memory circuit for n ≃100 was fabricated and the basic operation was confirmed at a temperature of 30 mK. This structure can be modified to operate with n = 1.
Recent research in fuzzy logic indicates a growing interest in practical and commercial applications. An improved fuzzy processor would embody both fuzzy (multilevel) and classical (binary) information processing in the same machine. One of the basic building blocks for the fuzzy processor is the fuzzy memory element. Such a circuit is proposed in the Letter.
A new simple analytical model for evaluating the programmed window of FLOTOX EEPROM cells at design level, for given programming waveforms and memory cell geometry, is proposed. The model enables optimisation of the memory cell geometry with respect to programmed window amplitude to be easily conducted, as well as correct selection of the programming conditions.
