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Digital storage

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  • Electrical and electronic engineering [3]
  • Circuit theory and circuits [3]
  • Electronic circuits [3]
  • Digital electronics [3]
  • Digital circuit design, modelling and testing [3]
  • Memory circuits [3]
  • Computer and control engineering [3]
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  • 2011 [3]

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A FPGA ray tracing scheme with memory optimization facility
Author(s): Huang Wei, Wan Wang Gen
Source: IET International Communication Conference on Wireless Mobile and Computing (CCWMC 2011), 2011, p. 329 - 334
Type: ConferencePaper
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This article presents a ray tracing acceleration system realized on FPGA platform. Additionally we make improvement to the memory accessing performance and achieve ideal ratio of performance against resources. Such work will gain ray tracing more applicable regions. The global scheme includes spatial indexing hierarchy module, ray generation module, pre-masking module, packet traversal module, arithmetic module and memory optimization facility which is described specially in this article..

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A spatial hierarchy FPGA implementation with DPR square root partitions
Author(s): Huang Wei, Wan Wang Gen
Source: IET International Communication Conference on Wireless Mobile and Computing (CCWMC 2011), 2011, p. 335 - 340
Type: ConferencePaper
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The customized hardware platform for spatial hierarchy construction with DPR square root partitions is validly obtained. Specialized process structures and storage structures are constructed to ensure the reutilization of presorting results on each level. The objective functions for division evaluation oriented to specific applications are scheduled. DPR partitions are built to meet intensive square root finding requests. After optimizations for algorithm and architecture, such achievement provides the starting points for future development.

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A 16nm SRAM design for low power and high read stability
Author(s): P. Saravanan, P. Kalpana
Source: 3rd International Conference on Advances in Recent Technologies in Communication and Computing (ARTCom 2011), 2011, p. 25 - 31
Type: ConferencePaper
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SRAM memory design in nanoscale regime has become increasingly challenging due to the reducing noise margins and increased sensitivity to threshold voltage variations. To overcome these challenges, different memory cells have been proposed for SRAMs with different transistor structures. These designs improve the cell stability in the subthreshold regime but suffer from bitline leakage noise, placing constraints on the number of cells shared by each bitline. In this paper, we propose a novel 11T SRAM cell topology which achieves cell stability as well as prevents bitline leakage. In addition to that, the proposed cell shows appreciable improvement in the dynamic power consumption. The HSPICE simulation and analysis at a 16nm feature size in CMOS process shows that the bitline leakage power consumption of the proposed 11T SRAM cell is reduced by 38% and the dynamic power consumption is reduced by 54% when compared to the existing 10T SRAM cell, while maintaining the read static noise margin nearly twice that of conventional 6T SRAM circuit.

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