Asynchronous circuits are inherently suitable for radiation-exposed environments due to their quasidelay insensitivity (QDI) and multirail logic systems. If an ionizing -radiation event is detected, the QDI property provides the ability to delay the current operation within the circuit until the effect has subsided. The dual -rail design provides additional support in this area because in many cases both rails must be affected in order for an SEU to occur. In addition to mitigating SEEs through asynchronous circuit -level architectures, radiation hardening techniques can be applied to transistor -level layout designs and circuit components, such as the DFF, for increased reliability.

As the transistor size scales down exponentially to nanometric dimensions, the susceptibility of electronic circuits to radiation increases drastically. Protection against the radiation is important in the field of biomedical, aerospace, communication and computing. Flip-flops (FFs) and static random access memories (SRAMs) are used to store the data in many critical applications where their performance must be resilient to radiation exposures to guarantee reliability. Therefore development of resilient FFs and SRAM are the challenging and demanding problems. In this chapter, different approaches are analysed to design these radiation hard circuits.

Area overhead reduction in conventional triple modular redundancy (TMR) by using approximate modules has been proposed in the literature. However, the vulnerability of approximate TMR (ATMR) in the case of a critical input, where faults can lead to errors at the output, is yet to be studied. Here, identifying critical input space through automatic test pattern generation and making it unavailable for the technique of approximating modules of TMR (ATMR) were focused, which involves a prime implicant reduction expansion. The results indicate that the proposed method provides 75–98% fault coverage, which amounts up to 43.8% improvement over that achieved previously. The input vulnerability-aware approach enables a drastic reduction in search space, ranging from 41.5 to 95.5%, for the selection of candidate ATMR modules and no compromise on the area overhead reduction is noticed.

A novel fault tolerant delay cell for ring oscillator (RO) is proposed. As RO is one of the crucial blocks in phased locked loop, delayed locked loo and clock data recovery, it should be tolerated against single event transient (SET) and stuck at faults for harsh environment. Their proposed hybrid fault tolerant topology is combination of triple and quad transistors redundancy, which is applied to the delay cell structure based on the sensitivity role of each transistor. The simulation results with Cadence software show that the proposed fault-tolerant delay cell dissipates 34.34 µW power, while it occupies 127.2 µm² chip area. The proposed topology not only has lower power dissipation in comparison with existing fault tolerant delay cells but also is more reliable against stuck at single and multiple faults and also SETs. By using the proposed reliable delay cell in the RO, the achieved power dissipation and phase noise are about 249 µW and −96 dBc/Hz, respectively, while higher reliability is achieved in comparison with non-redundant RO s.

Single-event transients (SETs) due to heavy-ion (HI) strikes adversely affect the electronic circuits in sub-100 nm regime in radiation environment. Time-to-digital converter (TDC) is an important electronic component in many fields such as space applications and is used for measuring time precisely as a digital value. In this study, the effect of SET due to radiation strike on 45 nm vernier-type TDC with a resolution of 7 ps is analysed using cadence spectre circuit simulator. When HI strikes the delay line of TDC close to the START/STOP pulse transition, it either widens or narrows the time interval to be measured, depending on whether it strikes the top/bottom voltage-controlled delay line (VCDL). Results show that the TDC is sensitive if the SET occurs during the transition of START/STOP pulse. Moreover, the change in the time interval occurs in a regular staircase pattern, if the VCDL is struck at all instants near the pulse transition. These errors lead to erroneous digital output and cause abrupt deviations in the staircase transfer characteristics of TDC. SETs in other constituent components of TDC such as D-flip-flop and priority encoder produces glitches which can be mitigated using existing guard gate technique.

Soft errors in semiconductor memories occur due to charged particle strikes on sensitive nodes. Technology and voltage scaling increased dramatically the susceptibility of static random access memories (SRAMs) to soft errors. In this study, the authors present AS8-SRAM, a new asymmetric memory cell that enhances the soft error resilience of SRAMs by increasing the cells critical charge. They run Simulation Program with Integrated Circuit Emphasissimulations and system level experiments to validate the AS8-SRAM cell characteristics at circuit level and evaluate the energy and reliability effectiveness of an AS8-SRAM-based cache memory. The authors’ results show that AS8-SRAM presents up to 58 times less failures in time compared to six-transistor SRAM. Moreover, based on embedded benchmarks experimentations, AS8-SRAM achieves up to 22% reduction in energy-delay product without any considerable loss in performance.

Operation of the 1-transistor, 1-capacitor dynamic random access memory cell that allows for two-bit operation, double the typical storage capacity, is explored. By using a metal-ferroelectric-semiconductor field-effect transistor, a second bit is captured in the ferroelectric layer polarisation resulting from negative and positive polarisation states. As a result, new modes of operation are created giving non-volatile, long-term storage as well as decreased power consumption and radiation hardening. A typical write and read operating cycle is outlined in-depth and used to verify operation indicating four distinct states representing the two bits. The resulting empirical data gives a comprehensive presentation of the read cycle of the memory cell. Methods for determining the polarisation state of the transistor are also explored and used to determine the average value for measured channel resistance using three types of transistors, each having different channel width and length.

As technology scales down, soft errors, because of single event upsets (SEUs) that affect multiple nodes (through multiple node charge sharing), become a serious concern in nanometre technology integrated circuits. Existing radiation hardening techniques provide partial or no immunity when more than one node are affected. A new latch topology is presented that guarantees soft error tolerance when a single node or any arbitrary combination of node pairs is affected by an SEU. The proposed scheme exploits a positive feedback loop which consists of C-elements. Simulation results validate the efficiency of the new design over existing soft error hardening techniques such as BISER, FERST and TPDICE.

The successful use of commercial-off-the-shelf (COTS) devices on board space applications requires the use of fault mitigation methods because of the effects of space radiation in microelectronics devices. This study describes a scheme for the random injection of single event transients/upsets to evaluate the viability of employing COTS field programmable gate array for an onboard, low-complexity, remote-sensing image data compressor. The fault injection features are added to the application to be tested by modifying its hardware description language source code. Then the tests are executed by simulation, with or without the inclusion of fault mitigation methods, so that comparative evaluations can be quickly obtained. The evaluation results (robustness enhancement against area) of different fault mitigation methods are presented, with good estimates of the behaviour of the hardware implementation of the application in a space radiation environment.

A collection of slides from the author's conference presentation is given. (25 pages)

A radiation hardened configuration bit cell design is proposed for an SRAM-based FPGA used in space application. The p-type gate poly on p-substrate structure provides a radiation immune resistor and a capacitor for RC hardened signal path. In addition to area efficiency, the proposed cell also overcomes the traditional linear energy transfer sensitivity to process and temperature variation.

The effect of trench-oxide depth on the α-particle-induced charge collection is analysed for various junction sizes. Simulation results indicate that the influence of trench-oxide depth on the charge collection substantially increases as the junction size is reduced. Confininement of the charge by the trench oxide in the reduced junction size is identified as a cause of this effect.

Static random-access memory (SRAM) based memories are widely used in electronic systems and if their contents change due to external reasons, the electronic system can functionally fail. One of the external reasons is the radiation induced soft errors as the SRAM memories are susceptible to radiation effects. Majority of the recently proposed methods use error correction codes (ECC) to mitigate soft errors. Error correction/detection capabilities of such methods are at most 3 bits in a codeword which will be insufficient while number of memory bits affected by a radiation particle is increased, as CMOS process technology shrinks towards around 5 nm. Since memory bits affected by a radiation particle are physically close, adjacent error detection/correction becomes a hot research topic. In this Letter, Euclidean geometry-low density parity check code, more capable ECC than Hamming code used in recent works, is explored in context of adjacent error detection performance. The results show that proposed method successfully detects up to 14-bit adjacent errors in a 15-bit codeword. As such, this method is suitable where high detection performance is needed. The proposed method is also simplified for efficient hardware implementation while detection performance is not sacrificed. Both methods are compared in terms of resource usage.

The development of space applications based on commercial system on chip (SOC) FPGA devices has become an important direction for the development of aerospace technology, but single event upsets (SEUs) in space is a difficult problem for commercial SOC FPGAs for space applications. This article presents an anti-anti method for ARM processors in SOC FPGA. This method makes full use of the hardware resources of dual-core ARM in SoC FPGA and improves the system's anti-SEU capability through dual-core mutual-check and recovery mechanisms. At the same time, the data stream and control flow fault tolerant are used to improve the anti-SEU capability within the processor. Error detection and correction (EDAC) and triple modular redundancy (TMR) are used to improve anti-SEU capability of the data flow. A two-level watchdog and ARM exception handling are used to achieve the anti-SEU capability of the control flow. Experimental results show that the two-level fault-tolerance mechanism proposed here improves the system's anti-SEU capability without adding additional hardware resources. This method is currently carrying out satellite-borne ground application verification.

There are a number of satellites working in the harsh space environment. The charged particles in space may strike the electron devices causing the undesired influences, such as soft errors in memory devices or permanent damage in hardware circuits. Aiming at reliability evaluation of very-large-scale integration circuits implemented in SRAM-based field programmable gate arrays, a fault injection platform is constructed based on the soft error mitigation controller in this study. The authors adopt a 16K-point fast Fourier transformation processor as the design under test (DUT) and inject errors into different positions. The effectiveness of this platform is varied by comparing the results of DUT with Golden data. Compared with the traditional reliability testing techniques, the fault injection method proposed in this study has the advantages of low cost, short test period and low resource consumption. Hence, the proposed fault injection design is suitable for circuits consuming huge resources and large number of repeating tests.