Radiation effects (semiconductor technology)
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- Abdus Sami Hassan [1]
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Area overhead reduction in conventional triple modular redundancy (TMR) by using approximate modules has been proposed in the literature. However, the vulnerability of approximate TMR (ATMR) in the case of a critical input, where faults can lead to errors at the output, is yet to be studied. Here, identifying critical input space through automatic test pattern generation and making it unavailable for the technique of approximating modules of TMR (ATMR) were focused, which involves a prime implicant reduction expansion. The results indicate that the proposed method provides 75–98% fault coverage, which amounts up to 43.8% improvement over that achieved previously. The input vulnerability-aware approach enables a drastic reduction in search space, ranging from 41.5 to 95.5%, for the selection of candidate ATMR modules and no compromise on the area overhead reduction is noticed.
This Letter proposes a low-cost, single event double-upset tolerant latch which utilises interlocked nodes to keep data, clock gating (CG) in Muller C-element (MCE) to turn off the storage cell, a three-input MCE to block the soft error from the storage cell and a weak keeper to prevent high impedance state. The storage cell in the proposed latch has better reliability than the conventional triple path dual-interlocked storage cell (TPDICE). Most up-to-date single event double-upset (SEDU) tolerant latches are carried out with too large cost penalties. The proposed one saves up to 93.32% area-power-delay product (APDP) compared with one up-to-date SEDU tolerant latch and even saves 36.36% APDP compared with only single event upset (SEU) tolerant latch in the referential. Simulation results have verified SEU and SEDU tolerance of the proposed latch.
A novel fault tolerant delay cell for ring oscillator (RO) is proposed. As RO is one of the crucial blocks in phased locked loop, delayed locked loo and clock data recovery, it should be tolerated against single event transient (SET) and stuck at faults for harsh environment. Their proposed hybrid fault tolerant topology is combination of triple and quad transistors redundancy, which is applied to the delay cell structure based on the sensitivity role of each transistor. The simulation results with Cadence software show that the proposed fault-tolerant delay cell dissipates 34.34 µW power, while it occupies 127.2 µm2 chip area. The proposed topology not only has lower power dissipation in comparison with existing fault tolerant delay cells but also is more reliable against stuck at single and multiple faults and also SETs. By using the proposed reliable delay cell in the RO, the achieved power dissipation and phase noise are about 249 µW and −96 dBc/Hz, respectively, while higher reliability is achieved in comparison with non-redundant RO s.
Radiations in harsh environments can significantly affects the performance of the silicon devices. Therefore, these effects should be taken into account in the system design phase. In this paper is shown the design of two high-speed drivers for optical Mach Zehnder modulators (MZM). The two drivers are designed to address the effects of low and high Total Ionization Dose (TID) levels, in the standard 65 nm CMOS technology. The target bit rate of the two drivers is 10 Gbps. The heavy effects that TID has on p-mosfets make the CMOS logic usable only for low radiation levels. Therefore, for TID levels higher than 10 Mrad the Current Mode Logic (CML) is more suitable. The use of this approach for the High TID driver allows reducing the effects of silicon damages. On the other hand, the CMOS driver allow halves the consumption power using only the 5% of layout area compared to the CML driver.
