In this work, the authors investigate analogue and radio-frequency (RF) figures-of-merit (FOM) of electrostatically-doped ferroelectric Schottky-barrier tunnel field-effect transistor (FET) (ED-FE-SBTFET) by deploying PZT (lead zirconium titanate) gate stack and dopant-free technology. This PZT gate stack results in negative capacitance behaviour as a result of the positive feedback among the electric dipoles within it. It realises an intrinsic amplifier to amplify the surface potential due to the applied gate bias and enhances the gate controllability significantly. As a result it facilitates lower ambipolar current, considerably high drive current and faster switching transitions. As the structure is realised by using dopant-free technique it ensures simplified fabrication process as it avoids the need of ion implantation and thermal annealing, reduces thermal budget. Here, a detailed comparison is carried-out between charge plasma Schottky-barrier tunnel FET and ED-FE-TFET for their high frequency FOMs such as cut-off frequency (), gain bandwidth product, transconductance generation factor and so on. The higher ratio of ED-FE-SBTFET reduces the static and dynamic both types of powers in digital circuits, while higher ratio ensures lower bias power of an amplifier.

Operation of the 1-transistor, 1-capacitor dynamic random access memory cell that allows for two-bit operation, double the typical storage capacity, is explored. By using a metal-ferroelectric-semiconductor field-effect transistor, a second bit is captured in the ferroelectric layer polarisation resulting from negative and positive polarisation states. As a result, new modes of operation are created giving non-volatile, long-term storage as well as decreased power consumption and radiation hardening. A typical write and read operating cycle is outlined in-depth and used to verify operation indicating four distinct states representing the two bits. The resulting empirical data gives a comprehensive presentation of the read cycle of the memory cell. Methods for determining the polarisation state of the transistor are also explored and used to determine the average value for measured channel resistance using three types of transistors, each having different channel width and length.

A negative capacitance field-effect transistor (FET) with sub-60 mV/decade subthreshold slope (SS) at different temperatures (i.e. 14.8 mV/decade at 300 K, 15.7 mV/decade at 360 K and 24.3 mV/decade at 400 K) is experimentally demonstrated. A detailed account of the fabrication process of a negative capacitor is first introduced, followed by the measurement setup for the negative capacitance FET. The impact of temperature on negative capacitance FETs is investigated: (i) the equation for the internal voltage gain in the FET as a function of temperature is derived using Gibbs free energy and (ii) internal voltage against gate voltage (V _Int against V _G), internal voltage gain against gate voltage (dV _Int/dV _G against V _G) and drain current against gate voltage (I _D against V _G) curves at different temperatures are measured. It is confirmed that internal voltage amplification can be achieved using the ferroelectric capacitor. However, the magnitude of the step-up voltage transformation is reduced, i.e. from 9.5 at 300 K to 2.6 at 400 K. Additionally, the SS is slightly increased (i.e. degrading from 14.8 mV/decade at 300 K to 24.3 mV/decade at 400 K) with increasing temperature; however, all SS values are better than the physical limits of SS as dictated by Boltzmann statistics.

A nonvolatile ferroelectric complementary metal-oxide-semiconductor (CMOS) circuit with both logic and memory functions is proposed as a new application of ferroelectric field effect transistors. The logic and memory operations of a NOT-logic ferroelectric CMOS device is demonstrated. Nondestructive readings of high and low output voltage levels of the device were performed. Data retention was measured up to10⁵ s (1.2 days).

A new FRAM design method utilising the bit-plate parallel cell architecture is presented. This method is effective in reducing circuit and layout overhead caused by on-pitch plate control circuitry. It also reduces the power consumption in memory array. Implementation results for a 0.13 µm, 512 kb FRAM prototype show that the memory block area in the proposed architecture is 15.6% less than that of the conventional structure.

A double-gate charge-plasma-based super-steep negative capacitance junctionless tunnel field effect transistor (NC-JLTFET) using a ferroelectric gate stack is proposed. Structurally, the NC-JLTFET consists of a heavily doped n-type silicon (Si) channel with two distinctive gates (control gate and fixed source gate). The fixed source gate accounts for the charge-plasma (hole plasma) formation which results in surrogate p-type doping by using work-function engineering. It induces a uniform p-region on the source side on the n-type doped Si film having a thickness less than the Debye length (L _D). The key attribute of the NC-JLTFET is the ferroelectric gate stack which is employed as a control gate resulting in NC behaviour due to positive feedback among the electric dipoles in the ferroelectric material. The NC-JLTFET endeavours to achieve a super-steep sub-threshold slope, a paramount boost in drive current and a substantial enhancement in peak transconductance (g _m) than the JLTFET. Meanwhile, it embraces the inherent advantages of the charge-plasma junctionless structure. Thus, it avails itself of a simple fabrication process flow and high immunity against process variations and random dopant fluctuations.

In this work, an enhancement mode dual gate ferroelectric gallium nitride metal oxide semiconductor-high electron mobility transistor (GaN MOS-HEMT) is proposed with enhanced linearity characteristics. The different DC characteristics of the device are analysed and compared with available experimental data of single gate un-recessed ferroelectric GaN MOS-HEMT. In order to analyse the linearity performance of the devices, a look up table-based large signal model is developed directly from technology computer-aided device simulation results built by feeding different small signal parameters. The different linearity characteristics such as input third-order intercept point (IIP3), the input gain compression point (P1dB), third-order intermodulation (IM3) and the carrier to intermodulation power ratio of both the devices are compared by harmonic balance simulation of the developed large signal models. The interlink between IIP3 and IM3 with transconductance indicates that the broader the transconductance distribution with respect to different gate voltage generates higher IIP3 and lower IM3, which results in an improved linearity performance. The dual gate device shows improved linearity performance resulting in applicability in radiofrequency front end receiver.