- Sort by:
- Newest first
- Titles A to Z
Filter by subject:
- Electrical and electronic engineering [2]
- Circuit theory and circuits [2]
- Electronic circuits [2]
- Digital electronics [2]
- Microprocessors and microcomputers [2]
- Computer and control engineering [2]
- Computer hardware [2]
- Circuits and devices [2]
- Microprocessor chips [2]
- Logic design and digital techniques [2]
- [2]
- http://iet.metastore.ingenta.com/content/subject/c5440,http://iet.metastore.ingenta.com/content/subject/a,http://iet.metastore.ingenta.com/content/subject/a8000,http://iet.metastore.ingenta.com/content/subject/a8700,http://iet.metastore.ingenta.com/content/subject/a8770,http://iet.metastore.ingenta.com/content/subject/b1265a,http://iet.metastore.ingenta.com/content/subject/b2000,http://iet.metastore.ingenta.com/content/subject/b2500,http://iet.metastore.ingenta.com/content/subject/b2570,http://iet.metastore.ingenta.com/content/subject/b6000,http://iet.metastore.ingenta.com/content/subject/b6100,http://iet.metastore.ingenta.com/content/subject/b6140,http://iet.metastore.ingenta.com/content/subject/b7000,http://iet.metastore.ingenta.com/content/subject/b7500,http://iet.metastore.ingenta.com/content/subject/b7510,http://iet.metastore.ingenta.com/content/subject/c5210,http://iet.metastore.ingenta.com/content/subject/c5260,http://iet.metastore.ingenta.com/content/subject/c5600,http://iet.metastore.ingenta.com/content/subject/c5610,http://iet.metastore.ingenta.com/content/subject/c5610s,http://iet.metastore.ingenta.com/content/subject/c7000,http://iet.metastore.ingenta.com/content/subject/c7300,http://iet.metastore.ingenta.com/content/subject/c7330
- c5440,a,a8000,a8700,a8770,b1265a,b2000,b2500,b2570,b6000,b6100,b6140,b7000,b7500,b7510,c5210,c5260,c5600,c5610,c5610s,c7000,c7300,c7330
- [2],[1],[1],[1],[1],[1],[1],[1],[1],[1],[1],[1],[1],[1],[1],[1],[1],[1],[1],[1],[1],[1],[1]
- /search/morefacet;jsessionid=2mswrxq278eyn.x-iet-live-01
- /content/searchconcept;jsessionid=2mswrxq278eyn.x-iet-live-01?facetOptions=2+3&option1=pub_concept&option2=author_facet&sortField=prism_publicationDate&pageSize=50&sortDescending=true&facetNames=author_facet+pub_concept_facet&value1=c5440&operator2=AND&value2=L.+Benini&operator3=AND&option3=pub_concept_facet&value3=
- See more See less
Filter by content type:
Filter by publication date:
Filter by author:
- L. Benini [2]
- A. Burg [1]
- A.Y. Dogan [1]
- D. Atienza [1]
- D. Bertozzi [1]
- J. Constantin [1]
In this study, the authors explore sequential and parallel processing architectures, utilising a custom ultra-low-power (ULP) processing core, to extend the lifetime of health monitoring systems, where slow biosignal events and highly parallel computations exist. To this end, a single- and a multi-core architecture are proposed and compared. The single-core architecture is composed of one ULP processing core, an instruction memory (IM) and a data memory (DM), while the multi-core architecture consists of several ULP processing cores, individual IMs for each core, a shared DM and an interconnection crossbar between the cores and the DM. These architectures are compared with respect to power/performance trade-offs for different target workloads of online biomedical signal analysis, while exploiting near threshold computing. The results show that with respect to the single-core architecture, the multi-core solution consumes 62% less power for high computation requirements (167 MOps/s), while consuming 46% more power for extremely low computation needs when the power consumption is dominated by leakage. Additionally, the authors show that the proposed ULP processing core, using a simplified instruction set architecture (ISA), achieves energy savings of 54% compared to a reference microcontroller ISA (PIC24).
Performance and power of gigascale systems-on-chip (SoCs) is increasingly communication-dominated. Designers have to accommodate the communication needs of an increasing number of integrated cores while preserving overall system performance under tight power budgets. State-of-the-art SoC communication architectures start facing scalability as well as modularity limitations, and more advanced bus specifications are emerging to deal with these issues at the expense of silicon area and complexity. Communication architecture evolutions mainly regard bus protocols (to better exploit available bandwidth) and bus topologies (to increase bandwidth). In the long run, more aggressive solutions are needed to overcome the scalability limitation, and networks-on-chip (NoCs) are currently viewed as a ‘revolutionary’ approach to provide a scalable, high performance and robust infrastructure for on-chip communication. The paper aims at surveying the evolution of the field, moving from SoC buses to forward-looking NoC research prototypes. The elements of continuity, as well as the key differences, will be captured, in an effort to extract general guiding principles in a fast-evolving domain.
