For the first time, the authors have investigated the analysis of the room-temperature operation of single-electron transistor (SET) for periodic symmetric functions (PSFs). They demonstrate that in SETs due to the Pauli exclusion principle the distance between current peaks against bias voltage in coulomb oscillations will be asymmetric. Also, because the separated energy levels have unequal tunnel-barrier resistance, different tunnelling current rates are obtained for each level. So, the unequal peak-to-valley current ratio (PVCR) will be observed in the coulomb oscillations, and therefore the operation of room-temperature of silicon SET-based PSFs is impossible.

At nanoscale grain boundaries and surface scattering effects lead to an increase of connecting wires electrical resistivity with decreasing wire dimensions. This increase of resistivity leads to significant power loss across connecting wires in nanocrossbars. In this study, the resistance of connecting wire as a function of material properties and feature size is calculated. Then the effect of the connecting wires resistance in phase change memory (PCM) performance in PCM-based passive nanocrossbar was evaluated. The performance metrics tested are: programmed resistance levels, programming duration, and energy consumption. Based on the simulation results, it was found that the power consumed in connecting wires decreases the power supplied to PCM cells. This reduction in power results in higher programmed low resistive state (R _ON). The effect of connecting wire resistance on PCM performance is studied as a function of the wire size, cell position on the nanocrossbar, and nanocrossbar size. Simulation results showed that the programmed R _ON is inversely proportional to feature size. Moreover, it increases up to almost 40%, with decreasing feature size to 40 nm. Moreover, programmed R _ON increases proportionally with increasing nanocrossbar size. Moreover, R _OFF/R _ON ratio drops almost 90% of targeted ratio at 1 kbit nanocrossbars. Furthermore, cells closer to supply sources are the least affected by wire resistance, while cells furthest from supply are the most affected. Finally, at the end of this study two methods are suggested to resolve the programmed R _ON reliability issue caused by energy drop across connecting wires.

This study presents a 0.35 µm silicon germanium bipolar complementary metal-oxide-semiconductor 10 Gb/s receiver circuit optimised for photonic–electronic three-dimensional integration. Measurements were conducted on a test-chip with a voltage-input signal, which was converted to a current via a series resistor. On the basis of measurement results and using the expected value of the photodetector responsivity of 1 A/W, the PAM-4 circuit consumes 145 mW, sensitivity is −21.8 dBm at 10 Gb/s, and at a bit error rate = 10⁻⁹.

Debugging and profiling tools can alter the execution flow or timing, can induce heisenbugs and are thus marginally useful for debugging time critical systems. Software tracing, however advanced it may be, depends on consuming precious computing resources. In this study, the authors analyse state-of-the-art hardware-tracing support, as provided in modern Intel processors and propose a new technique which uses the processor hardware for tracing without any code instrumentation or tracepoints. They demonstrate the utility of their approach with contributions in three areas - syscall latency profiling, instruction profiling and software-tracer impact detection. They present improvements in performance and the granularity of data gathered with hardware-assisted approach, as compared with traditional software only tracing and profiling. The performance impact on the target system – measured as time overhead – is on average 2–3%, with the worst case being 22%. They also define a way to measure and quantify the time resolution provided by hardware tracers for trace events, and observe the effect of fine-tuning hardware tracing for optimum utilisation. As compared with other in-kernel tracers, they observed that hardware-based tracing has a much reduced overhead, while achieving greater precision. Moreover, the other tracing techniques are ineffective in certain tracing scenarios.