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IEE Proceedings I (Solid-State and Electron Devices)

Volume 132, Issue 6, December 1985

Volumes & issues:

Volume 132, Issue 6

December 1985

Editorial. Power semiconductor devices
High-voltage high-current GTO thyristors
GTO with monolithic antiparallel diode
  • Author(s): E. Huang  and  J.P. Barnes
  • Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 132, Issue 6, p. 245 –247
  • DOI:  10.1049/ip-i-1.1985.0054
  • Type: Article
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  • p. 245 –247 (3)
    The integration of a monolithic antiparallel diode into the inactive cathode bond-pad area of a gate turnoff thyristor (GTO) has been investigated with computer modelling followed by experimental work, using as a vehicle the BTV60, a 120A GTO optimised for AC motor control. It is shown that this is feasible and is especially suitable for second generation GTO technology (fine interdigitation, unshort-circuited anode, lightly gold-killed), with the diode having the right characteristics in forward voltage drop and reverse recovery. The resulting devices performed well in tests and may lead to considerable simplification and cost reduction in motor control circuits.
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A model for MOS transistors
  • Author(s): G.S. Bhatti ; B.K. Jones ; P.C. Russell
  • Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 132, Issue 6, p. 248 –252
  • DOI:  10.1049/ip-i-1.1985.0055
  • Type: Article
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  • p. 248 –252 (5)
    A model is presented for the operation of MOS transistors which is applicable to many power and short channel devices. This improved 1-dimensional charge control model allows for the effects of the mobility reduction due to the gate-channel field and to velocity saturation of the channel carriers under the high drainsource field. Experiments have verified the model for n and p channel devices. The high drain voltage ID/VG data are compared with the model predictions using accepted experimental values of the bulk saturation velocity and velocity-field curves together with experimental measurements of the channel series resistance and the gate-field reduction of the mobility.
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One-dimensional numerical simulation of complementary power Schottky structures
The performance of high-voltage field relieved Schottky barrier diodes
50 A 1200 Vn-channel IGT
  • Author(s): H. Yilmaz ; L.-S. Chen ; W.R. Van Dell ; J. Benjamin ; M. Chang ; K. Owyang
  • Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 132, Issue 6, p. 261 –263
  • DOI:  10.1049/ip-i-1.1985.0058
  • Type: Article
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  • p. 261 –263 (3)
    A 1200 V n-channel insulated gate transistor (IGT) has been designed and evaluated. To reduce the Miller capacitive coupling of the input and the output terminals during the transient conditions, the terraced gate design has been implemented. As a result, the Miller capacitance is lowered 4–5 times compared to conventional gate design. Also, the gate pad is placed at the centre of the pellet so that the intrinsic device turnon and turnoff times can be shorter. To prevent current crowding and thermal fatigue around a single emitter pad, a multiple emitter pad design scheme is adopted. The 1200 V n-IGTs have reached up to 114 A latch-up current at 150°C.
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Power devices in gallium arsenide
Erratum: An accurate and simple technique of determination of the maximum power point and measurement of some solar cell parameters
Asymptotes for boundary determined current density of PIN diodes
  • Author(s): J. McGhee ; I.A. Henderson ; M. Saffari
  • Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 132, Issue 6, p. 272 –276
  • DOI:  10.1049/ip-i-1.1985.0061
  • Type: Article
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  • p. 272 –276 (5)
    A general boundary determined equation is used to obtain the physical asymptotes for the current density of PIN diodes. Application of this equation indicates that lower level injection regions are degenerate versions of the higher level regions. Other methods depend upon precise knowledge of the carrier density profile whereas the present approach only requires a notional indication of the ratio of minimum to boundary carrier densities. This ratio is an important determining factor for the gradient of boundary carrier density which exerts a strong influence upon boundary current density. A theoretical basis is laid which explains the link between the various ranges of injection level. This asymptotic approach could provide an effective method in applying charge control models for transient analysis over wide ranges of current.
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A brief analysis of the transient forward voltage drop in fast diodes
Characterisation and modelling of SIPOS on silicon high-voltage devices
  • Author(s): J.N. Sandoe ; J.R. Hughes ; J.A.G. Slatter
  • Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 132, Issue 6, p. 281 –284
  • DOI:  10.1049/ip-i-1.1985.0063
  • Type: Article
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  • p. 281 –284 (4)
    The paper describes the way a semiconducting coating, such as SIPOS, controls the spread of the depletion region near the surface of simple planar high-voltage diodes. This is important to achieve the optimum breakdown performance for high-voltage devices. When an insulating oxide separates the SIPOS from the silicon, the surface layer acts as a resistive field plate and spreads a thin depletion region right across the surface at only a few volts reverse bias. Without the oxide, or if it is thin enough to be effectively transparent to electrons and holes, the depletion region spread in the surface is limited by current flow across the SIPOS silicon interface, and the depletion spread with bias becomes more like that expected for bulk silicon. For reverse biased planar diodes, with SIPOS directly over the junction, the leakage current is proportional to the voltage to the power of 0.7–0.8 when measured at temperatures where the current through the SIPOS dominates. These effects can be modelled, neglecting any effect from the p–n junction, using lateral and vertical SIPOS-silicon interface current measurement data.
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A numerical analysis of the resurf diode structure
  • Author(s): P. Walker ; J.T. Davies ; K.I. Nuttall
  • Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 132, Issue 6, p. 285 –290
  • DOI:  10.1049/ip-i-1.1985.0064
  • Type: Article
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  • p. 285 –290 (6)
    The results of a 2-dimensional numerical analysis of medium and high-voltage diode structures that incorporate a ‘resurf’ field reduction layer are presented. The work illustrates the effect of surface charge on the optimisation of the design and indicates the requirements that will ensure bulk breakdown for a wide range of surface charge densities. The results are used to assess the analytical design equation presented by Appels et al., modified to take account of surface charge. A comparison is also made with results obtained from an analysis of the field limiting ring technique, and the relative performance of the two methods is assessed.
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A double etched profile for improved breakdown voltage in pn-junctions: theory and practice
  • Author(s): A.T. Plumpton  and  K.J. Haydock
  • Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 132, Issue 6, p. 291 –294
  • DOI:  10.1049/ip-i-1.1985.0065
  • Type: Article
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  • p. 291 –294 (4)
    A poorly designed geometry at the junction edge can severely limit the blocking capability of high voltage pn-junctions. The work presented involves the design of a double groove where we attempt to spread the electric field along the plateau region formed between two grooves. This leads to reduced surface field values, giving enhanced voltage breakdown. Although the value of the peak electric field is dependent on the depth of the shallow etch, it is shown that the allowable tolerance in this depth is approximately 10%, making this design a viable proposition for production.
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