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IEE Proceedings I (Solid-State and Electron Devices)

Volume 130, Issue 3, June 1983

Volumes & issues:

Volume 130, Issue 3

June 1983

VLSI
Comparison of MOS processes for VLSI
Modelling of small MOS devices and device limits
  • Author(s): Pallab K. Chatterjee ; B.S. Ping Yang ; B.E. Hisashi Shichijo
  • Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 130, Issue 3, p. 105 –126
  • DOI:  10.1049/ip-i-1.1983.0023
  • Type: Article
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  • p. 105 –126 (22)
    The paper reviews the various approaches to the modelling of small-geometry MOS devices. The physics and interaction of device properties in small MOSFETs are discussed as they apply to device and circuit design for VLSI. It is shown that statistical fluctuation of device geometry and the effect of parasitics is the primary determinant of circuit performance. Scaling theory for MOSFETs and limits to scaling are examined in the context of geometry and high-field effects. It is concluded that the incentives to scale geometries below 0.5 μm are small.
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High-density one-device dynamic MOS memory cells
  • Author(s): B.S. Kiyoo Itoh  and  B.S. Hideo Sunami
  • Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 130, Issue 3, p. 127 –135
  • DOI:  10.1049/ip-i-1.1983.0024
  • Type: Article
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  • p. 127 –135 (9)
    Performance of one-device cells for dynamic random-access memories is described in terms of signal, noise, speed, soft error and process complexity. From an examination of areal layout and cross-section, five kinds of cells used in commercially available 64 Kbit DRAMs are compared, placing stress on the concept of the folded-data and open-data lines. Somes new DRAM cell concepts, such as a vertically structured capacitor, are proposed on the basis of the paper. The future application limit of the one-device cell seems to exist in the optical lithography of the next generation DRAM of 1 Mbit and beyond, not in the device concept itself.
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Submicron MOS process with 10:1 optical-projection printing and anisotropic dry etching
  • Author(s): W. Müller ; W. Beinvogl ; L. Risch ; R. Sigusch
  • Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 130, Issue 3, p. 136 –143
  • DOI:  10.1049/ip-i-1.1983.0025
  • Type: Article
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  • p. 136 –143 (8)
    Results of an n-MOS process with minimum feature sizes in the submicron range are reported. Lithography is realised by 10:1 optical printing with step-and repeat exposure. Minimum linewidths of 0.7μm have been achieved using a high numerical aperture projection optics with 0.42NA. In order to obtain high fidelity in pattern transfer, anisotropic dry-etching techniques have been used for all levels. Results are given for the patterning of the TaSi2In+-poly stack, and an aluminium etching process with BCl3/Cl2 is discussed in detail. Reducing the gate oxide thickness to 12.5nm, transistors have been optimised forminimum short-channel effects down to 0.5μm channel length. The limiting gate and drain voltages for the submicron devices have been determined. For a supply voltage of 3 V, negligible long-term transistor degradation is extrapolated. The effect of scaling of the lateral dimension on the field isolation and contact hole resistance is investigated. Exploratory dynamic RAM cell arrays with a cell area 37 μm2 and a cell capacitanceof 36 fF have been fabricated and characterised.
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New hot-carrier injection and device degradation in submicron MOSFETs
  • Author(s): E. Takeda ; Y. Nakagome ; H. Kume ; S. Asai
  • Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 130, Issue 3, p. 144 –150
  • DOI:  10.1049/ip-i-1.1983.0026
  • Type: Article
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  • p. 144 –150 (7)
    New kinds of hot-carrier injection mechanisms, which are different from channel hot-electron and substrate hot-electron injection mechanisms already reported by Ning, et al., are presented. These are first drain avalanche hot-carrier (DAHC) injection and secondly substrate current induced hot-electron (SCHE) injection. DAHC injection is due to the emission of electrons and holes heated in the drain avalanche plasma. SCHE injection is caused by the emission of excess electrons originating from impact ionisation of substrate current. The authors have succeeded in directly observing these two injection phenomena by measuring gate current as low as of the order of 10−15 A for small size MOS devices having effective channel length below 1.0 μm and gate oxide thinner than 10nm. The measured gate currents due to both injection mechanisms are also modelled numerically using the CADDET, a 2-D analysis program. In addition, device degradation due to these new injections is clarified. Base on the experimendal results, it is shown that DAHC effect rather than channel hot-electron effect, is more responsible for hot carrier related device degradation. The SCHC is also found to cause significant threshold shift, even at the VD<3V bias condition. thus, the presented injection phenomena prove to impose more Severe constraints on the submicron VLSI device design.
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Transit and storage times of bipolar transistors in a VLSI environment
  • Author(s): S.S. Rofail
  • Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 130, Issue 3, p. 151 –152
  • DOI:  10.1049/ip-i-1.1983.0027
  • Type: Article
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  • p. 151 –152 (2)
    The main objective of the work is to study the effects of the physical and technology parameters on the delay times of bipolar transistors in a VLSI environment. Expressions for the transit time in a very narrow base, and the storage time due to the minority charge in the emitter region will be derived. The analysis will be performed using typical substrate (which is the emitter in I2 L structures having zero epitaxial width) profiles, obtained from measurements. The results and conclusions can be used to tailor an optimum impurity profile that gives minimum storage time.
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