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Volume 129
Issue 2
IEE Proceedings I (Solid-State and Electron Devices)
Volume 129, Issue 2, April 1982
Volumes & issues:
Volume 129, Issue 2
April 1982
Noise figure for mesfet with delta-function doping profile
- Author(s): N.P. Maxfield ; J.E. Stitch ; P.N. Robson
- Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 129, Issue 2, p. 41 –50
- DOI: 10.1049/ip-i-1.1982.0006
- Type: Article
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The minimum noise figure for a MESFET with a delta-function doping profile along the substrate interface is calculated using an analytical method and a two-dimensional computer simulation. The results are compared with similar results obtained for a uniformly doped device. For typical GaAs FETs the minimum noise figure is not improved. However, at the minimum noise point the transconductance is higher, compensating for the increased source-gate capacitance there.
Electron-Beam Technology in Microelectronic Fabrication
- Author(s): D.R. Brambley
- Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 129, Issue 2, page: 50 –50
- DOI: 10.1049/ip-i-1.1982.0007
- Type: Article
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VHSIC Technologies and Tradeoffs
- Author(s): P.B. Denyer
- Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 129, Issue 2, page: 50 –50
- DOI: 10.1049/ip-i-1.1982.0008
- Type: Article
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New amorphous-silicon electrically programmable nonvolatile switching device
- Author(s): A.E. Owen ; P.G. Le Comber ; G. Sarrabayrouse ; W.E. Spear
- Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 129, Issue 2, p. 51 –54
- DOI: 10.1049/ip-i-1.1982.0009
- Type: Article
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The paper reports preliminary data on the characteristics of a new electronic switching device based on amorphous silicon structures. The device is polar, and is switched from OFF to ON (WRITE) or ON to OFF (ERASE) by voltages opposite signs; the threshold voltage for the WRITE operation is 4 –8 V, depending on the device, and for ERASE it is ̃ 1 V. The OFF and ON resistances are typically l MΩ, and in the range 50–300Ω, respectively. Experimental devices have been switched through 105 WRITE and ERASE cycles, and the prospects are that this could be considerably increased. Particularly notable features of the new memory device are its extremely fast transition times (100 ns or less for both the WRITE or ERASE operations) and the very low energy involved in the switching transition (<10−6 J). Present results indicate that the threshold voltages are only slightly dependent on temperature.
Reduction of carrier reflection effects in a silicon MBE p+-s-n+ device using cascaded end regions
- Author(s): S Ramanan and D. Kakati
- Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 129, Issue 2, p. 55 –57
- DOI: 10.1049/ip-i-1.1982.0010
- Type: Article
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The results of a steady-state numerical analysis of thin p+-n-n+ devices in silicon are reported. Successful fabrication of such devices by MBE has recently been reported in the literature. Asymmetric doping of the end regions causes either of the carrier types (majority or minority) to dominate the forward current. Both the carriers are reflected by the opposite junctions. The reflection of the dominant carriers has a pronounced effect on the forward current in low- and medium-level injections. To investigate further the junction reflection properties, devices with cascaded end regions are analysed. It is found that on making the reflecting end region a cascade of two steps, of concentrations 1×1018 cm-3 and 1 × 1016 cm-3, respectively, the forward current increases by more than 50% in typical operating regions.
Novel p-n junction polysilicon dual-gate mosfet for analogue applications
- Author(s): K.V. Anand and S.G. Chamberlain
- Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 129, Issue 2, p. 58 –60
- DOI: 10.1049/ip-i-1.1982.0011
- Type: Article
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Fabrication details and experimental data are given for a dual-input-gate p-channel enhancementmode MOSFET, which can be used for analogue applications. The device employs a novel gate structure in which a single-level polysilicon gate is laterally segmented along the channel length by means of alternate p+ and n+ doping, thus considerably simplifying the technology. It is proposed that the outer gates be used as the input terminals. Both practical and theoretical results for the static output characteristics are given, together with the relevant AC parameters, e.g. the forward conductance of the two gates and the input impedance between the gate terminals. Satisfactory w-channel devices, with n+-p+-n+ segmented gates, were also fabricated, and data from these are also given.
C mosfet model for analogue circuit simulation employing process-empirical parameters
- Author(s): G. Cardinali ; S. Graffi ; M. Impronta ; G. Masetti
- Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 129, Issue 2, p. 61 –66
- DOI: 10.1049/ip-i-1.1982.0012
- Type: Article
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In the design of linear MOS integrated circuits, transistor models must be accurate in the saturation region, but the excellent fitting in the linear region obtainable with sofisticated physical models and modelling of short-channel effects are less important. Besides, in many of the available MOST models, the so-called physical parameters are, in practice, evaluated from fitting procedures on measured device characteristics, and so a fully empirical point of view may as well be adopted in chosing model equations. By exploiting these considerations, better trade-offs between accuracy and ease of parameter acquisition can be obtained. In the paper we present a simple empirical MOST model which accounts for mobility reduction and channel-length modulation in MOS devices with dimensions suitable for analogue applications. It is proved that the proposed model is no less accurate in the CAD of linear circuits than other more elaborate models, but it is more simple as far as parameter acquisition is concerned. Finally, it is shown that the model provides differential parameters which are reasonably accurate, and that it can be successfully employed in the CAD of MOS analogue integrated circuits.
Yield enhancement realised for analogue integrated filters by design techniques
- Author(s): Karl Knauer and Pfleiderer Hans-Jörg
- Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 129, Issue 2, p. 67 –71
- DOI: 10.1049/ip-i-1.1982.0013
- Type: Article
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In the fabrication of analogue integrated circuits the yield depends on the tolerances and defect density in mask generation and device fabrication. Yield optimisation, therefore, has to resolve two conflicting requirements. Whereas to reduce the influence of tolerances the device area has to be large, the larger the device area chosen, the higher will be the possible defect number. To determine the optimum device area with respect to yield in the fabrication of CCD transversal filters, the tolerances in mask generation and fabrication have first to be analysed. Tolerances that are constant in a device can be eliminated by ‘design cleverness’. The way in which the influence of statistical tolerances can be reduced by design centring will be demonstrated with reference to an implemented device. To determine the total yield it is further necessary to take into account the influence of defects. The optimum device area from the aspect of yield can then be determined as a function of both tolerance and defect density.
Casmos – an accurate MOS model with geometry-dependent parameters: I
- Author(s): R.E. Oakley and R.J. Hocking
- Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 129, Issue 2, page: 71 –71
- DOI: 10.1049/ip-i-1.1982.0014
- Type: Article
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Electrical and optical equivalence of switching in v-groove punch-through-mode mist
- Author(s): R.B. Calligaro and A.G. Nassibian
- Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 129, Issue 2, p. 72 –76
- DOI: 10.1049/ip-i-1.1982.0015
- Type: Article
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The V-gioove punch-through-mode metal-insulator (tunnel)-silicon thyristor (MIST) is examined under electrical and optical base simulation. Electrical switching was obtained by base current injection and optical switching by 0.6328 μm radiation. Using a simple model, modified to take into account area effects and optical excitation, it is shown that the electrically and optically switched MIST are mutually equivalent, thus verifying the conclusions derived from a recent theoretical study.
Book review: Large Scale Integration (Devices, Circuits and Systems)
- Author(s): H. Ahmed
- Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 129, Issue 2, page: 76 –76
- DOI: 10.1049/ip-i-1.1982.0016
- Type: Article
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76
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Bistable operation and spectral tuning of injection laser with external dispersive cavity
- Author(s): V.Yu. Bazhenov ; A.P. Bogatov ; P.G. Eliseev ; O.G. Okhotnikov ; G.T. Pakf ; M.P. Rakhvalsky ; M.S. Soskin, ; V.B. Taranenko ; K.A. Khairetdinov
- Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 129, Issue 2, p. 77 –82
- DOI: 10.1049/ip-i-1.1982.0017
- Type: Article
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Spectral tuning of an AlGaAs-GaAs laser with external dispersive cavity, operating in a singlefrequency regime, has been studied. The dependence of output power on wavelength was shown to have the shape of a hysteresis loop, which indicates the existence of bistable operation. Such a behaviour in a laser is due to the existence of a composite cavity comprised of a laser-diode intrinsic cavity and an external dispersive cavity. The refractive index of a semiconductor medium depends on the inversion population, and, since the inversion population depends on the radiation intensity this causes optical nonlinearity of the active diode region. As a result, such an optical laser scheme becomes analogous to the well known optical bistable systems, including a Fabry-Perot interferometer with optical nonlinearity.
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