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Volume 127
Issue 1
IEE Proceedings I (Solid-State and Electron Devices)
Volume 127, Issue 1, February 1980
Volumes & issues:
Volume 127, Issue 1
February 1980
Noise figure of m.e.s.f.e.t.s
- Author(s): C.R. Brewitt-Taylor ; P.N. Robson ; J.E. Sitch
- Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 127, Issue 1, p. 1 –8
- DOI: 10.1049/ip-i-1.1980.0001
- Type: Article
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The noise figure of a m.e.s.f.e.t. is calculated as a function of drain current using the gradual channel approximation and the Shockley impedance-field technique. The results are conveniently presented as a single universal family of curves with no adjustable empirical factors. The analytical results are compared with those from a 2-dimensional computer simulation.
Topological and experimental analysis of stationary behaviour of transferred-electron devices with nonuniform geometry
- Author(s): H. Tateno and S. Kataoka
- Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 127, Issue 1, p. 9 –14
- DOI: 10.1049/ip-i-1.1980.0002
- Type: Article
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A study is made of topological and experimental analysis of stationary behaviour of transferredelectron devices of uniform doping concentration with nonuniform geometry. Such and analysis is useful in the understanding and estimating of the static characteristics of GaAs m.e.s.f.e.t.s, microwave amplifiers and fast switching devices. It is shown that it is possible for the devices to exhibit negativ conductance, including switching between terminals, provided that the cross-sectional area increases steeply toward the anode, and the doping concentration is higher than a critical value; and that this results from the formation of a stationary high-field domain around the expanded part. The theoretical result is experimentally confirmed with GaAs devices.
Current gain in bipolar transistors with a field plate over the base surface
- Author(s): V. Anantharam and K.N. Bhat
- Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 127, Issue 1, p. 15 –19
- DOI: 10.1049/ip-i-1.1980.0003
- Type: Article
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Vertical n-p-n and lateral p-n-p transistor structures of an integrated circuit are studied using an electrolytic tank analogue and it is shown that the presence of a proper field plate extending from the collector-base junction over most of the base surface will improve the current-gain factor considerably. Experimental results of the analogue study, simulating typical carrier lifetimes and typical overall dimensions, are presented with various geometrical dimensions as parameters.
Measurement of lifetime of photoinjected carriers in solar cells by reverse voltage pulse response
- Author(s): S.R. Dhariwal
- Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 127, Issue 1, p. 20 –24
- DOI: 10.1049/ip-i-1.1980.0004
- Type: Article
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Transient response of p-n junction solar cells under constant illumination is studied by applying a reverse voltage pulse. It is shown that, by a proper choice of current in the external circuit, results similar to those in open-circuit voltage-decay method or reverse-voltage recovery method could be obtained. Thus an extremely simple circuit allows lifetime determination by keeping the cell under normal illuminated conditions.
Electrothermal transients due to self heating in a silicon p-n diode
- Author(s): W.J. Stepowicz and W. Janke
- Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 127, Issue 1, p. 25 –28
- DOI: 10.1049/ip-i-1.1980.0005
- Type: Article
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The method of calculating the junction-temperature response and the nonisothermal transient i/v characteristics for a silicon forward-biased p-n diode is presented in this paper. The proposed method is based on the iterative calculation procedure, in which a diode is assumed to be subjected to a current or voltage waveform. This is in contrast with other methods, in which a temperature-indepenmdent power-input function, seldom met in practice, is assumed. As an example, calculations of the voltage across the diode and of the junction temperature for some given current inputs i(t) have been performed according to the presented method, and the results are discussed.
Investigation of Ar ion implant gettering of gold in silicon by m.o.s. and Rutherford backscattering techniques
- Author(s): A.G. Nassibian and B. Golja
- Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 127, Issue 1, p. 29 –36
- DOI: 10.1049/ip-i-1.1980.0006
- Type: Article
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The gettering of Au in silicon has been investigated using m.o.s. techniques and Rutherford backscattering. Silicon wafers were intentionally contaminated with Au, and then Ar ion implant was performed on the back surface of the wafer and the damaged layer annealed at 1050°C for times of 15 and 60 minutes. Comparison of generation lifetime between gold wafers and gold implant-gettered wafers, obtained from the response of m.o.s. capacitors to a linearly varying voltage showed a marked improvement for the implant gettered wafers. Rutherford backscattering using 14N+ ions was carried out on the wafers, both on the implant damaged layer and on some 30–40μm in the bulk of the material. The Au concentration in the implant damaged layer was higher than in the bulk of the same wafer for both anneal times, indicating that Au had been effectively gettered. The backscattering speetra also showed other impurities such as Br, Cu, Fe, Sb, Sn and Te present in higher concentration in the implant damaged layer than in the bulk
Predeposition through a polysilicon layer as a tool to reduce anomalies in phosphorus profiles and the push-out effect in n-p-n transistors
- Author(s): M. Finetti ; G. Masetti ; P. Negrini ; S. Solmi
- Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 127, Issue 1, p. 37 –41
- DOI: 10.1049/ip-i-1.1980.0007
- Type: Article
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The carrier concentration profiles obtained after the diffusion of phosphorus through a thin polycrystalline silicon film into a silicon substrate are investigated. It is shown that it is possible, by performing the predeposition process at 1000°C or 920°C, to avoid or greatly lower the high-diffusivity tail usually present in phosphorus profiles. It is also reported that, in sutable experimental conditions, predepositions through a polycrystalline layer reduce the push-out effect under the emitter of n-p-n bipolar transistors. The results are explanined on the basis of an interstitial-phosphorus-difussion mechanism in silicon, and by supposing that the excess of interstitials generated by the ingoning p atoms is partially adsorbed at the grain boundareis of the polycrystalline film.
A thin-film transistor with polytetrafluoroethylene as insulator
- Author(s): A. De Vos and B. Hindryckx
- Source: IEE Proceedings I (Solid-State and Electron Devices), Volume 127, Issue 1, p. 42 –44
- DOI: 10.1049/ip-i-1.1980.0008
- Type: Article
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The fabrication and performance characteristics of a new kind of thin-film transistor is presented. The novelty consists of the use of a thin polymer film as an insulator between gate and semiconductor film. The insulator used is polytetrafluoroethylene film, evaporated by an electron gun. The semiconductor used is a tellurium film, evaporated by resistive heating. The transistor shows useful current/voltage characteristics, but the isulator and the insulator – semiconductor interface show slow-drift phenomena, analogous to the drift seen in most conventional thin-film transistors with an inorganic insulator film.
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