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1887

IEE Proceedings G (Circuits, Devices and Systems)

Volume 140, Issue 3, June 1993

Volumes & issues:

Volume 140, Issue 3

June 1993

Digitally tunable MOS-current mirrors for high precision applications
Fundamental topologies of three-phase LC resonators and their applications for oscillators
  • Author(s): R. Rabinovici ; B.Z. Kaplan ; D. Yardeni
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 3, p. 148 –154
  • DOI:  10.1049/ip-g-2.1993.0024
  • Type: Article
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  • p. 148 –154 (7)
    There exists an increasing need in power electronics for efficient three-phase inverters. They can find application in power control of AC motors or as an intermediate stage in DC-DC converters. It seems that employing three-phase oscillators for such inverters can be an appropriate solution. However, for the sake of efficiency and also simplicity, it should be beneficial that the three-phase oscillators will consist of high-Q three-phase resonators. The present paper describes several circuits that can be entitled three-phase resonators. The discussion is mainly related to the topological structures of the systems. A numerical simulation of their dynamics is also given. The three-phase resonators consist of six reactors (three inductors and three capacitors), and not merely of three as might have been expected. This is probably due to the duality existing in electromagnetics. Active elements are added mainly for sustaining the oscillations. However, a further task for them is to assist in balancing the three-phase system. Some of the models are advantageous since they have in inherent property to constrain the DC bias in the three-phase variables, both in the currents and in the voltages, to zero.
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Distributed parameter analysis of dark I–V characteristics of the solar cell: estimation of equivalent lumped series resistance and diode quality factor
  • Author(s): A. Vishnoi ; R. Gopal ; R. Dwivedi ; S.K. Srivastava
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 3, p. 155 –164
  • DOI:  10.1049/ip-g-2.1993.0025
  • Type: Article
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  • p. 155 –164 (10)
    The present investigation deals with the distributed parameter analysis of the p–n junction solar cell in the current-induced case at low level injection. The theory, for the first time, takes into account the metal–semiconductor contact resistance, along with the base bulk resistance and the diffused layer shear resistance. The transcendentally nonlinear differential equations for the emitter layer current and voltage have been solved analytically. Additionally, expressions for the I–V characteristic and equivalent ‘lumped’ series resistance have been established. Such physical parameters are very useful in the optimisation of the contact finger width and separation. Inclusion of the contact resistance, even for very small values, corresponds to the nonuniform carrier generation within the metallic grid. Therefore, the results are affected both qualitatively and quantitatively. The most important effect has been calculated in the I–V characteristics resulting from an additional contribution to the series resistance. Analysis reveals that the series resistance and the diode quality factor vary with applied current.
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Design of biquad filters with a single current follower
  • Author(s): S.-I. Liu ; J.-J. Chen ; H.-W. Tsao ; J.-H. Tsay
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 3, p. 165 –170
  • DOI:  10.1049/ip-g-2.1993.0026
  • Type: Article
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  • p. 165 –170 (6)
    Five new configurations of single current–follower–biquad (SCFB) filters are presented. They can synthesise second-order highpass, lowpass, bandpass, allpass, and notch filtering functions using a single current follower connected to four or more passive one-port RC elements. We have calculated the active and passive sensitivities to evaluate the circuit performance. The natural frequencies and the quality factors of most resulting SCFB filters will be insensitive to the current tracking error of the current follower. Experimental results which agree with theoretical analysis are obtained.
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Statistical and behavioural modelling of analogue integrated circuits
  • Author(s): T. Koskinen  and  P.Y.K. Cheung
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 3, p. 171 –176
  • DOI:  10.1049/ip-g-2.1993.0027
  • Type: Article
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  • p. 171 –176 (6)
    A full statistical model for the behavioural parameters of an analogue cell is presented. The parameter variations with respect to manufacturing tolerances are approximated by response surfaces which allow the mean, standard deviation, correlation of parameter pairs and the actual distribution to be estimated. The parameters are characterised from either measurements of fabricated devices or from circuit simulation of the analogue cell. An efficient method of mapping between the performance space and the behavioural parameter space which requires no a priori assumption about the analytical maping is demonstrated. By combining the mapping with statistical methods we can include tolerance information in the behavioural model. Such models can then be used for simulation and yield estimation at a higher circuit level. This procedure is demonstrated on the behavioural model of a switched-capacitor integrator by considering the effect of tolerances derived from both simulations and actual measurements. The accuracy of results obtained with the characterised behavioural model relative to the circuit-level simulation is considered.
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Speed optimised array architecture for flash EEPROMs
  • Author(s): A.A.M. Amin
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 3, p. 177 –181
  • DOI:  10.1049/ip-g-2.1993.0028
  • Type: Article
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  • p. 177 –181 (5)
    The paper describes a new architecture for a split-gate flash EEPROM memory array. The new array architecture provides increased speed and less susceptibility to soft writes during read operations. A unique circuit design and operation method obviates the need for applying high erase voltage in the path between the memory array and the sense amplifier. This allows all the transistors in this speed path to be fabricated as low voltage minimum channel length devices, thereby increasing their speed of operation and consequently the speed of the memory device as a whole. The new architecture, however, requires the addition of two extra rows of nonmemory cell transistors in addition to following a strict programming sequence to guard against spurious programming of unselected cells.
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Analytical design formulation for minority-carrier well-type guard rings in CMOS circuits
  • Author(s): M.-J. Chen ; C.-Y. Huang ; P.-N. Tseng
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 3, p. 182 –186
  • DOI:  10.1049/ip-g-2.1993.0029
  • Type: Article
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  • p. 182 –186 (5)
    Minority carriers injected from an active emitter into the substrate and partially collected by the bottom well junction in an epitaxial CMOS structure are studied. Two-dimensional numerical simulation has revealed that the minority-carrier collection current along the bottom well junction is contributed primarily by two mechanisms: the first due to minority carriers injected into a layer between the upper collecting plate and the bottom reflecting plate; and the second due to those penetrating the high/low junction and then spreading out in the large, highly-doped bulk as in the nonepitaxial case. Based on this observation, a new analytic model for the minority-carrier escape current has been developed as a measure of well-type guard ring efficiency. This model, including a closed-form expression as function of epitaxial layer thickness, well junction depth and guard ring width, has been confirmed by experimental data as well as by two-dimensional numerical simulation. As predicted by the model, the measured escape current has been found to be dominated by the second mechanism for the case of well junction depth close to epitaxial layer thickness while the first mechanism has been identified to dominate the escape current measured from the structure having sufficient epitaxial layer thicknesses.
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Minimal realisation of recursive and nonrecursive three-dimensional systems
Design of frequency-mode set-valued logic networks
  • Author(s): T. Aoki ; Y. Yuminaka ; T. Higuchi
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 3, p. 191 –198
  • DOI:  10.1049/ip-g-2.1993.0031
  • Type: Article
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  • p. 191 –198 (8)
    A set-valued logic network is proposed to provide a potential solution to the interconnection problems in VLSI systems. The fundamental concept is frequency multiplexing of logic values for the increase of information density in logic networks. It is shown that the set-valued logic network can be constructed with two basic building blocks realised by frequency-selective circuits. A set-valued switching algebra is introduced for the systematic synthesis of networks. The setvalued logic network thus obtained has the attractive features of high information density, highly parallel structure and extensibility into ultrahigher-valued logic systems.
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Very high sample rate digital filters using the δ operator
  • Author(s): R.M. Goodall  and  B.J. Donoghue
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 3, p. 199 –206
  • DOI:  10.1049/ip-g-2.1993.0032
  • Type: Article
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  • p. 199 –206 (8)
    The paper reports upon the theoretical and practical issues concerned with achieving digital filters in which the sample rate is very much higher than the dominant frequency, illustrated by means of a general-purpose second-order digital filter section which can readily be configured for lowpass, highpass, bandpass or bandreject operation over a range of frequencies. The δ operator approach is used throughout, although a brief comparison is included to show what the implications would be of using the z operator. The paper shows how full performance can be achieved even with four orders of magnitude between the filter frequency and the sampling frequency, including practical results from implementation using a DSP device.
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Very high linearity tunable OTA in 5 V CMOS
Area-efficient diminished-1 multiplier for Fermat number-theoretic transform
  • Author(s): S. Sunder ; F. El-Guibaly ; A. Antoniou
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 3, p. 211 –215
  • DOI:  10.1049/ip-g-2.1993.0034
  • Type: Article
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  • p. 211 –215 (5)
    A novel VLSI implementation of diminished-1 multipliers is proposed. The new implementation obviates the need for code translation from diminished-1 into regular binary representation and, consequently, a reduction in the required chip area is achieved. For a multiplier where the modulus involved is F4, the fifth Fermat number, a reduction of about 16% in the chip area, is achieved relative to that required by the conventional diminished-1 multiplier. Diminished-1 multipliers are indispensable for the implementation of Fermat number transforms.
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Finite element modelling of multielectrode capacitive systems for flow imaging
  • Author(s): S.H. Khan  and  F. Abdullah
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 3, p. 216 –222
  • DOI:  10.1049/ip-g-2.1993.0035
  • Type: Article
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  • p. 216 –222 (7)
    The CAD of a complex multielectrode arrangement for flow imaging is explored using the finite element method (FEM). This electrode arrangement forms the primary sensor subsystem for an electrical capacitive tomography (ECT) system. Results are presented in the form of sensor's performance parameters as functions of its various geometric parameters. The performance parameters include the standing and normalised capacitances, ratio of the maximum to minimum capacitance of the sensor (Kc) and the sensor's spatial sensitivity distributions. Extensive computer simulation studies were undertaken in calculating these parameters, and the techniques in finite element (FE) model definition, mesh generation and refinement, error minimisation and checking are highlighted in the paper in relation to the effective and efficient use of the FEM. Detailed results for a particular sensor design are compared with an experimental prototype and found to give good agreement. The response of the sensor to various flow regimes is also presented and analysed to optimise its performance for image reconstruction.
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Improved design of digital filters satisfying a combined loss and delay specification
  • Author(s): S. Lawson  and  T. Wicks
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 3, p. 223 –229
  • DOI:  10.1049/ip-g-2.1993.0036
  • Type: Article
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  • p. 223 –229 (7)
    The classical solution to the design of both analogue and digital filters with magnitude and delay constraints is to cascade a minimum phase circuit satisfying the magnitude constraint and an allpass circuit that equalises the delay distortion caused by the first. Such a solution is inefficient and, in this paper, a simple method is considered whose aim is to meet both constraints simultaneously in the digital case. The filter model that is used is a parallel arrangement of allpass circuits which allows a large range of transfer functions to be realised. This model is efficient in the sense that the number of multipliers required equals to the filter order. A sequential quadratic programming technique coupled with a single-line template is used to find the set of coefficients which minimises the squared error. A novel way of setting up the frequency grid is proposed which aims to increase the loss quickly in the transition band. The choice of suitable starting points has an important impact on the length of the optimisation process. A particularly efficacious choice is presented here. Examples are provided illustrating the method, including lowpass, bandpass and multiple bandpass designs, as well as comparing it with a recently reported technique.
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New approach to automatic symbolic analysis of electric circuits
Author's reply: New approach to automatic symbolic analysis of electric circuits
Reply: New approach to automatic symbolic analysis of electric circuits

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