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IEE Proceedings G (Circuits, Devices and Systems)

Volume 140, Issue 2, April 1993

Volumes & issues:

Volume 140, Issue 2

April 1993

Perpendicular transport properties of a p-GaAs/δ-doped superlattice/n+-GaAs structure
  • Author(s): W.-C. Liu ; C.-Y. Sun ; D.-F. Guo ; R.-C. Liu
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 2, p. 81 –84
  • DOI:  10.1049/ip-g-2.1993.0012
  • Type: Article
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  • p. 81 –84 (4)
    The perpendicular transport properties of a p-GaAs/δ-doped superlattice/n+-GaAs structure were studied at 300 and 77 K. An interesting S-shaped negative differential resistance (NDR), resulting mainly from avalanche multiplications within the superlattice region, was observed at 300 K. A different multistate NDR phenomenon and an interesting hysteresis behaviour were found at 77 K. The multistate NDR is attributed to a sequential subavalanche multiplication process occurring within superlattice periods; holes created by avalanche multiplications play an important role in the transport properties. The hysteresis behaviour at 77 K seems to be caused by the heavily accumulated holes, which cannot react synchronously with the applied electric field.
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Capacitor switched gate-turnoff thyristor
  • Author(s): Q. Huang  and  G.A.J. Amaratunga
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 2, p. 85 –90
  • DOI:  10.1049/ip-g-2.1993.0013
  • Type: Article
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  • p. 85 –90 (6)
    Gate-turnoff performance of the gateturnoff thyristor (GTO) through the transient current of a capacitor is studied. Experimental results on such a capacitor-switched GTO (CSG) show that a large negative transient current is obtained resulting from the discharge of a capacitor attached to the gate of the GTO. Very high turnoff current in the CSG can be achieved. A simple MOS-controlled gate-driving circuit is proposed which provides full voltage control of the GTO. Comparison between the CSG and the GTO-cascode switch is also carried out.
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Odd-degree elliptic-function lower-sideband polylithic crystal filters
Neural network approach to spectral estimation of harmonic processes
  • Author(s): G. Martinelli  and  R. Perfetti
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 2, p. 95 –100
  • DOI:  10.1049/ip-g-2.1993.0015
  • Type: Article
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  • p. 95 –100 (6)
    A neural network approach is presented for the spectral estimation of random processes composed of closely spaced sinusoids in white noise. A linear programming formulation is adopted, determining the minimum L1-norm solution of a set of linear constraints. Then, the optimisation problem is solved by a dedicated electrical neural network whose input is the estimated autocorrelation of the process, and whose output is the power spectrum. The time response is very fast since the network is analogue and has parallel architecture. Moreover the lack of a learning phase makes it suited both to real-time signal processing and to VLSI implementation. Results of SPICE simulations are presented.
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SEESIM: a fast synchronous sequential circuit fault simulator with single-event equivalence
  • Author(s): C.P. Wu ; C.L. Lee ; W.Z. Shen
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 2, p. 101 –105
  • DOI:  10.1049/ip-g-2.1993.0016
  • Type: Article
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  • p. 101 –105 (5)
    The paper presents a concept of single event equivalence to be used in the sequential circuit fault simulator. The concept dynamically identifies the equivalent faults for a simulated pattern. It combines advantages of the fanout-free region, critical path tracing and the dominator concept, which were applicable only to combinational circuit fault simulation. The implemented fault simulator, SEESIM, based on the concept, demonstrated a performance superior to that of a state-of-the-art concurrent fault simulator, and comparable to that of parallel-pattern single-fault propagation simulators. It requires a minimal amount of memory and, because of its simplicity, can be easily extended to multilogic or higher level simulation.
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Peak power tracking in parallel connected convertors
  • Author(s): K. Siri ; V.A. Caliskan ; C.Q. Lee
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 2, p. 106 –116
  • DOI:  10.1049/ip-g-2.1993.0017
  • Type: Article
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  • p. 106 –116 (11)
    In this paper, a control scheme for parallel connected convertor systems, which will transfer the maximum available power from a nonideal voltage source, is presented. Monitoring the rates of change in both the average input current and average input power from the source, the proposed control method can dynamically regulate the DC-DC convertor system to track the peak power point of the source. The amplitude and frequency of the oscillations due to a limit cycle around the system peak power point is analysed. To improve the system efficiency and reliability, the central limit distribution control is incorporated into the proposed scheme to uniformly distribute the supplied power among the parallel connected convertors.
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Design and analysis of a high-speed sense amplifier for single-transistor nonvolatile memory cells
  • Author(s): A.A.M. Amin
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 2, p. 117 –122
  • DOI:  10.1049/ip-g-2.1993.0018
  • Type: Article
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  • p. 117 –122 (6)
    A novel high-speed sense amplifier for use with nonvolatile single-transistor memory cells is described. Using a current-sensing scheme and novel circuit techniques, the amplifier achieves sensing speeds equal to or better than those achievable by memory arrays using two transistors per cell. Other circuit techniques were used to improve the circuit-noise immunity as well as sensitivity to critical mask misalignments including the use of output latches, dummy bit lines and decoded odd/even reference-memory-cell selection. The circuit was implemented on a 32 k EPROM memory chip using 1.5 µmN-well CMOS process.
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Sensitive differential method for the extraction of the mobility variation in uniformly degraded MOS transistors
  • Author(s): O. Roux-dit-Buisson ; G. Ghibaudo ; J. Brini
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 2, p. 123 –126
  • DOI:  10.1049/ip-g-2.1993.0019
  • Type: Article
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  • p. 123 –126 (4)
    A new method for the exploitation of the characteristics of uniformly degraded MOS transistors is proposed. The method, which is based on a first order differential analysis of the shift observed in the Id(Vg) transfer characteristics after stress, enables an accurate determination both of the threshold voltage shift and of the mobility variation to be accurately obtained as a function of stress (e.g. injection dose). The method has been tested on Fowler—Nordheim stressed MOSFETs and this enabled us to demonstrate that the mobility is not a monotonous function of the interface charge created after stress, and, therefore, that no unique value for the Coulomb scattering coefficient can be extracted
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Effective heuristic algorithms for VLSI circuit partition
  • Author(s): L. Tao  and  Y.C. Zhao
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 2, p. 127 –134
  • DOI:  10.1049/ip-g-2.1993.0020
  • Type: Article
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  • p. 127 –134 (8)
    The paper studies the multiway graphpartition problem for VLSI circuit partition. Given a graph representing a VLSI circuit, the graph vertices are partitioned into mutually exclusive subsets to minimise the total weights for edges crossing the subsets under the constraint that the vertex weights are evenly distributed among the subsets. Simulated annealing and tabu search are adapted to solve this problem based on a special neighbourhood design. A new general optimisation paradigm, called stochastic probe, is then proposed to integrate the advantages of the above two approaches. Extensive experimental study shows that all three new algorithms produce significantly better solutions than the LPK algorithm reported by Lee, Park and Kim, and that the stochastic probe algorithm always produces the best solution among all the four algorithms with a running time comparable with that for the LPK algorithm.
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Efficient systolic solution for a new prime factor discrete Hartley transform algorithm
  • Author(s): P.K. Meher ; J.K. Satapathy ; G. Panda
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 2, p. 135 –139
  • DOI:  10.1049/ip-g-2.1993.0021
  • Type: Article
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  • p. 135 –139 (5)
    Recently, a novel systolic structure has been proposed for the computation of DFT for transform length N = 4M, M being prime to 4. In this paper, we have proposed a similar structure for the computation of DHT by prime factor decomposition. A new recursive algorithm is also proposed for computing DHT using a linear systolic array of cordic processing elements. The proposed structure has nearly the same hardware requirement as that of the corresponding DFT structure for real-valued data; but it yields significantly higher throughput.
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Residual current device with high immunity to nuisance tripping
  • Author(s): P.V. Brennan
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 140, Issue 2, p. 140 –144
  • DOI:  10.1049/ip-g-2.1993.0022
  • Type: Article
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  • p. 140 –144 (5)
    Residual current devices, though offering a high degree of protection from fire and electric shock hazards, are notoriously prone to nuisance tripping. Efforts have been made to counter the problem primarily by the use of simple time delays, with a moderate degree of success. This paper presents two techniques that greatly reduce the vulnerability to nuisance tripping: phase detection to eliminate sensitivity to capacitive leakage and a more elaborate two-stage time delay to reducevulnerability to transients. Results obtained with a prototype design are presented to confirm theimprovement in performance
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