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IEE Proceedings G (Circuits, Devices and Systems)

Volume 139, Issue 4, August 1992

Volumes & issues:

Volume 139, Issue 4

August 1992

Compatibility of switched capacitor filters with VLSI processes
Design of zero-phase spherically symmetric N-dimensional IIR digital filters
  • Author(s): C. Charalambous  and  M.M. Saleh
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 4, p. 419 –426
  • DOI:  10.1049/ip-g-2.1992.0068
  • Type: Article
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  • p. 419 –426 (8)
    The paper presents a new method for designing zero-phase N-dimensional IIR digital filters satisfying given amplitude design specifications. The method is based on applying the N-dimensional extension of McClellan transformation to the square of a one-dimensional IIR digital filter design recently proposed by Charalambous. The resulting N-dimensional digital filter is of zero-phase and hyperspherically symmetric but unstable. Stabilisation of the filter is achieved by dividing it into a product of 2N filters, each of which is stable if realised through a recursion in the suitable quadrant. The stabilisation procedure uses the properties of the complex cepstrum. Three examples are introduced to show the performance and validity of the design method presented. The designs obtained are also tested in image processing applications.
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Simple methods for the design of 2D recursive digital filters with noncircular cutoff boundary
  • Author(s): M. Ahmadi ; A. Mazinani ; M. Shridhar ; V. Ramachandran
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 4, p. 427 –437
  • DOI:  10.1049/ip-g-2.1992.0069
  • Type: Article
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  • p. 427 –437 (11)
    The paper presents several methods for the design of 2D filters with noncircular cutoff boundaries. One-dimensional filters are used as the main building block and other building blocks are formed by various transformations. It is shown that cascading an appropriate number of these building blocks will yield a 2D filter approximating to the desired cutoff boundary. The proposed methods are very simple and require no optimisation. However, optimisation techniques are also utilised if higher accuracies are needed. Examples are given to illustrate the uses of the proposed techniques.
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Recursive Hartley filter — a new efficient digital-prefilter structure
  • Author(s): J.-C. Liu  and  T.-P. Lin
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 4, p. 438 –444
  • DOI:  10.1049/ip-g-2.1992.0070
  • Type: Article
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  • p. 438 –444 (7)
    Generation of various prefiltering characteristics from the recursive Hartley filter (RHF) is introduced. The RHF can be regarded as a new family of digital-prefilter structures and is the only prefilter proposed to have the ability to design the lowpass, bandpass and highpass digital filters simultaneously. These prefilters can be combined with appropriately designed equalisers based on equiripple methods, leading to efficient FIR digital-filter designs. In the bandpass design, the RHF is further modified to have a linear phase property and a more efficient hardware structure. The characteristics of the RHF and modified RHF are discussed in detail and those applied to the prefilter-equaliser approach are demonstrated in several design examples. Compared with the conventional equiripple design the proposed RHF and modified RHF can provide significant savings in the number of multipliers and adders at the expense of slightly larger filter length (delays).
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Associative memory integrated circuit based on neural mutual inhibition
  • Author(s): S.M.S. Jalaleddine  and  L.G. Johnson
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 4, p. 445 –449
  • DOI:  10.1049/ip-g-2.1992.0071
  • Type: Article
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  • p. 445 –449 (5)
    Hardware associative or content-addressable memory (CAM) which finds in one operation the nearest match to input data among several templates is very crucial in the design of effective pattern recognition systems. We call this type of memory a relaxative CAM (RCAM) as opposed to the traditional exact-match CAM design. A compact implementation of an RCAM calls for the employment of a neural network model. In the paper we present the design and silicon implementation of an RCAM using a neural mutual inhibition network as the relaxation circuit. Spice simulations of the mutual inhibition and the RCAM performance are presented. A 16-word 12-bit IC has been fabricated through MOSIS using 2 μm double-metal CMOS technology. The RCAM chip was tested and its correct functionality has been fully verified.
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Design of switched-capacitor FIR filters with application to a low-power MFSK receiver
  • Author(s): A. Da̧browski ; U. Menzi ; G.S. Moschytz
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 4, p. 450 –466
  • DOI:  10.1049/ip-g-2.1992.0072
  • Type: Article
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  • p. 450 –466 (17)
    Finite impulse response (FIR) switched-capacitor (SC) filters for minimum frequency-shift keying (MFSK) demodulation techniques have been developed and are discussed. The proposed filters comprise combinations of the following building blocks: sample-and-hold circuits, even-odd delay circuits, Gillingham delay circuits, recharge memory elements, Lee-Martin summer circuits, recharge summer circuits, and rotator switches. These are described in the paper. Furthermore, composite SC filter structures are derived using a morphological approach. The FIR SC filter structures are compared and evaluated with respect to the required chip area when implemented in 3 μm CMOS technology, and, by computer simulation, with regard to bit error probability when used in an MFSK receiver. It is shown that the receiver performance is independent of the FIR filter structure used. Furthermore, using the FIR filters, and for a given bit error probability, the required signal-to-noise ratio (SNR) is actually 3 dB lower than for a typical commercial MFSK receiver (e.g. an MB87002).
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Parameter identification approach to fault diagnosis of switched capacitor circuits
Exact noise figure of a noisy two-port with feedback
  • Author(s): V.M.T. Lam ; C.R. Poole ; P.C.L. Yip
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 4, p. 473 –476
  • DOI:  10.1049/ip-g-2.1992.0074
  • Type: Article
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  • p. 473 –476 (4)
    Exact expressions for the noise figure of a two-port with shunt or series feedback are presented in terms of standard four-noise parameters and imittance parameters. The general case of an arbitrary feedback network, characterised in terms of a two-port imittance matrix, is analysed and the results are applied to the more practical case of a single lossless feedback element. The results are presented in the form of the standard two-port noise figure equation, with additional terms which illustrate clearly the effect of feedback. The equations presented make use of directly measurable device parameters, and are therefore design-oriented.
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Specification of error amplifiers for use in feedforward transmitters
Generalised approach to automatic custom layout of analogue ICs
  • Author(s): D.J. Chen  and  B.J. Sheu
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 4, p. 481 –490
  • DOI:  10.1049/ip-g-2.1992.0076
  • Type: Article
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  • p. 481 –490 (10)
    An automatic custom analogue IC layout methodology is presented which employs primitive cell recognition, critical net analysis, and self-constructive floorplanning and routing techniques. Based on this methodology, a general-purpose analogue circuit module layout generator, SLAM, has been developed. Given the schematic netlist of an arbitrary analogue MOS circuit module, SLAM can quickly generate a high-quality custom layout to some desired aspect ratio. With a simple extension of the hierarchy, this method can also handle more complex analogue subsystems. Special layout constraints are automatically analysed for each analogue circuit and properly incorporated into the layout generation on each level of the circuit hierarchy to achieve both high performance and overall area efficiency. Experimental results on common analogue VLSI building blocks such as operational amplifier, comparator and neural circuit modules are presented.
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Voltage-mode and current-mode Sallen-Key implementations based on translinear conveyors
  • Author(s): A. Fabre  and  J.-L. Houle
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 4, p. 491 –497
  • DOI:  10.1049/ip-g-2.1992.0077
  • Type: Article
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  • p. 491 –497 (7)
    The simulation results of two Sallen-Key bandpass implementations with standard operational amplifiers are compared and discussed. The implementation using a voltage follower as a controlled source compares favourably with the one using equal valued passive components. Voltage-mode and current-mode Sallen-Key implementations from translinear conveyors with unity gain are described. The filters use five passive components so that the quality factor Q can be adjustable from one of them, without varying ω0. Simulation results are given and discussed.
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100 Mbit/s adaptive data compressor design using selectively shiftable content-addressable memory
  • Author(s): S. Jones
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 4, p. 498 –502
  • DOI:  10.1049/ip-g-2.1992.0078
  • Type: Article
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  • p. 498 –502 (5)
    A hardware architecture for an adaptive loss-less data compressor is described. The architecture is suitable for implementation on a single ASIC. The architecture results from an investigation aimed at developing novel compression algorithms that can utilise the fine-grain parallel processing capabilities of VLSI integrable structures and hence, achieve high performance. The efficiency of different hardware structures are assessed for text, image and machine code data compression through simulation. Suitable candidate designs based around a shifting content-adressable memory (CAM) array are identified. A design for one such option is developed using a commercial CAD package. Despite using modest 2 μM CMOS technology, compressed data is produced at a minimum rate of 100 Mbit/s. Details of the design are presented
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Class of undetectable stuck-open branches in CMOS memory elements
  • Author(s): A. Rubio ; S. Kajihara ; K. Kinoshita
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 4, p. 503 –506
  • DOI:  10.1049/ip-g-2.1992.0079
  • Type: Article
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  • p. 503 –506 (4)
    The paper considers a class of undetectable stuck-open faults in CMOS circuit branches and shows that in basic static latch and flipflop circuits some branches are of this class. Moreover, undetectable stuck-open faults in transistors reported in recent works pertain to this class. It is shown that, in the case of stuck-open faults in these branches, the static circuit becomes a dynamic one. Because most of the undetectable stuck-open faults in branches (or transistors) in sequential memory elements are of this class, a general approach for DFT for these faults are proposed, and examples of fully detectable circuits are presented.
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Resistively variable capacitors using general impedance convertors
  • Author(s): A. Carlosena ; D. Müller ; G.S. Moschytz
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 4, p. 507 –516
  • DOI:  10.1049/ip-g-2.1992.0080
  • Type: Article
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  • p. 507 –516 (10)
    The use of general impedance convertors (GICs) for the realisation of resistively variable capacitors (RVCs) is demonstrated. Such elements are useful in analogue-adaptive circuits and for neural networks. Various design concepts have been examined with the aim of finding configurations that are suitable for discrete, and complete, or partial VLSI realisation. A number of useful circuit topologies have been found. Design guidelines are given; simulations and experimental results are compared. The resulting circuits are being considered for use in adaptive telephone hybrid networks for high-speed full-duplex data transmission.
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Theory and design of LDI lattice digital and switched-capacitor filters
  • Author(s): B. Nowrouzian
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 4, p. 517 –526
  • DOI:  10.1049/ip-g-2.1992.0081
  • Type: Article
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  • p. 517 –526 (10)
    The paper presents a new method for the exact design and synthesis of lossless discrete-integrator (LDI) lattice digital and switched-capacitor (SC) filters. In the proposed design method, the entire digital and SC filter synthesis is performed directly in the discrete-time z-domain without any recourse to the concept of a continuous-time analogue prototype reference filter. Two LDI lattic e digital filter structures are proposed, one of which employs a Foster-type and the other a Cauer-type (leapfrog) configuration. Both of these structures require at most n+1 digital multipliers and n+1 unit delays, where n represents the order of the transfer function to be realised. Similarly, the corresponding LDI lattice SC filters require at most n+2 operational amplifiers (single- or double-ended). A practical example is given to illustrate the design method and to compare the hardware requirement and the magnitude-frequency response sensitivity in the passband of the LDI lattice digital and SC filters with those of the corresponding bilinear LDI ladder digital and SC filters. It is shown that the proposed lattice filters exhibit superior sensitivity features despite their low hardware requirements.
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Performance trade-offs of globally clocked data-driven arrays
  • Author(s): A. Spray  and  S. Jones
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 4, p. 527 –533
  • DOI:  10.1049/ip-g-2.1992.0082
  • Type: Article
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  • p. 527 –533 (7)
    The support of digital signal processing and control algorithms within cellular arrays is well established. The algorithms that tend to be supported are those with a high degree of homogeneity; however, there are many functions that involve feedback loops and conditionality and, topologically, this can lead to irregular layouts which require resynchronisation mechanisms to ensure that data arrive at the correct processors at the correct times. This paper studies a novel method for effecting this resynchronisation. The strategy presented has hardware simplicity, speed and throughput rate close to those of globally clocked systolic arrays, while also having the programming simplicity and the tolerance to data-dependent communication of data-driven arrays. The strategy shown possesses the unusual feature that the adoption of slower individual processing elements can lead to overall faster algorithmic throughput rates. The paper further demonstrates this effect using arbitrary algorithms on a linear array of processors and an array with a feedback loop where both the array size and the data-driven processing element size were altered.
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Go/no-go testing of analogue macros
On the design of VLSI arrays for discrete Fourier transform
  • Author(s): C.-M. Liu  and  C.-W. Jen
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 4, p. 541 –552
  • DOI:  10.1049/ip-g-2.1992.0084
  • Type: Article
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  • p. 541 –552 (12)
    In this paper the design of VLSI arrays for discrete Fourier transform (DFT) is investigated through three topics: (i) algorithm exploitation, derivation and analysis, (ii) array realisation, and (iii) schemes to calculate arbitrarily long length DFT using a reasonable sized array. Four DFT systolic algorithms are examined and compared in terms of computing parallelism and computational complexity. Among the four algorithms, one is newly proposed. The new one exhibits much higher computing parallelism and lower computational complexity than the other three, but is applicable when the DFT length is prime. Based on the four algorithms, seven systolic arrays and seven two-level pipelined systolic arrays are devised. The outstanding features of these arrays are that the number of I/O channels is independent of the DFT length and the time overhead in manipulating consecutive data bundles are eliminated. Two schemes are presented to calculate long-length DFT using arrays with a reasonable number of processing elements. Performance of different algorithms, arrays and schemes is compared and summarised in six tables to serve as the selection criteria for different applications.
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Low-voltage BICMOS and vertical OTA

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